附录一、英文原文Hardware/Software Design and Development ProcessEverett Lumpkin and Michael GabrickDelphi Corporation, Electronics and Safety DivisionINTRODUCTIONProcess and technology advancements in the semiconductor industry have helped to revolutionize automotive and consumer electronics. As Moore’s Law predicted, the increase in complexity and operating frequencies of today’s integrated circuits have enabled the creation of system applications once thought to be impossible. And systems such as camera cell phones, automotive infotainment systems, advanced powertrain controllers and handheld personal computers have been realized as a result.In addition to the increases in process technology, the Electronic Design Automation (EDA) industry has helped to transform the way semiconductor integrated circuits (IC) and subsequent software applications are designed and verified. This transformation has occurred in the form of design abstraction, where the implementation continues to be performed at higher levels through the innovation of design automation tools.An example of this trend is the evolution of software development from the early days of machine-level programming to the C++ and Java software written today. The creation of the assembler allowed the programmer to move a level above machine language, which increased the efficiency of code generation and documentation, but still tied the programmer to the underlying hardware architecture. Likewise, the dawn of C / C++ compilers, debuggers and linkers helped to move the abstraction layer further away from the underlying hardware, making the software completely platform independent, easier to read, easier to debug and more efficient to manage.However, a shift to higher levels of software abstraction has not translated to a reduction in complexity or human resources. On the contrary, as integrated systems have become more feature rich, the complexity of the operating system and corresponding applications have increased rapidly, as have the costs associated with the software implementation and verification activities. Certainly the advancements in embedded software tools such as static code checkers, debuggers and hardware emulators have helped to solve some of the software verification problems, but software verification activities have become more time and resource consuming than the actual software creation. Time-to-market constraints have pushed software verification activities to the system-level, and led to a greater demand for production hardware to be made available earlier inthe software development flow.As with the software case, the semiconductor design community has made a very similar transformation in their design and verification strategies sparked by advances in the EDA community. Designs that were once implemented completely at the transistor level migrated to the gate-level implementation through the development of schematic capture tools. The creation of hardware description languages such as Verilog and VHDL and the corresponding compilers, simulators and synthesis tools allowed hardware designers to move away from the gate-level implementation to the register transfer level (RTL). The EDA community is now promoting even higher levels of abstraction, often under the banner of electronic system level design (ESL) . Again, this represented a fundamental change in design abstraction, which allowed the designers to think in terms of overall functionality instead of the configuration of gates needed to implement the desired functionality.As Application Specific Integrated Circuit (ASIC) design complexities have grown and the process geometry continued to shrink, the manufacturing and NRE costs for silicon has increased rapidly. For example, the cost for silicon mask sets range from $50,000 for a simple ASIC to greater than $1,000,000 for an advanced microprocessor or microcontroller . The high costs associated with ASICs underscores the motivation of the hardware community to insure that the intended functionality is implemented correctly prior to taking a design to silicon. The EDA industry has helped this cause by providing sophisticated verification tools that prove the high-level design and the silicon implementation will function equivalently. However, even with these tools available, more than ½ of all IC and ASIC designs require a re-spin of silicon, where 70% of the re-spins are due to logic or functional errors that verification efforts should have caught . With the huge investment required for each re-spin, system level verification is becoming a focus of the overall hardware verification strategies.Although we have seen significant advancements in the processes of hardware and software design during the past two decades, surprisingly, there have been little advancements made at the system level. Today’s system process consists of the paper study of the proposed hardware architecture, required functionality, microprocessor throughput, memory configuration, and the potential hardware migration paths. The process has remained relatively unchanged. Furthermore, the software implementation is typically held off until hardware prototype units are created, placing the software developers and system verification teams at a disadvantage. This current approach has many drawbacks including: slow adaptation to changes in customer requirements, drawn out hardware and software integration, limitations in system debugging, and difficulties meeting the time-to-market constraints.This paper presents a new approach to system-level design through the creation of a virtual system, which allows for an early analysis of hardware and software interaction while removing many of the drawbacks plaguing traditional system development. This paper also presents a virtual automotive air-bag system implementation and explores the benefits of virtual system development.PARADIGM SHIFTThe motivation for system level design and analysis is to significantly improve productivity through a paradigm shift that allows hardware and software to be designed concurrently rather than serially. Productivity is thus enhanced by the elimination of re-work, increased quality of the final system, improved verification, and shorter time-to-market.As design trends continue to move to higher levels of abstraction, more emphasis will continue to be placed in verification activities at both the component and system level. The creation of a “virtual” system using accurate models of the hardware provides engineers with the following benefits: an architectural exploration of hardware and software functions, the creation of flexible prototype hardware, more accurate analysis of throughput and portability, software development earlier in the cycle, and rapid debugging through the instrumentation of the virtual hardware.One of the primary advantages of a virtual system implementation is architecture exploration, which is the process of determining an optimum solution to a design space problem. Take for example the two-dimensional architectural space shown in Figure 1. The two design parameters shown (typically there are many design parameters) are power consumption and clock speed, with the ideal solution illustrated by the center of the target. In this simplified example, the yellow cross illustrates a hardware prototype ECU that exceeds the ideals for power consumption and fails to meet the clock speed ideals. Because of the time-to-market constraint, the system architecture continues to be based upon the initial hardware prototype without adequate exploration of alternative choices. The end result of a hardware based development process is a suboptimum product that may miss the design targets.Conversely the green crosses show an alternative path to the optimum design solution. Several virtual systems are assembled and tested in the same time-to-market window. The final virtual system is on-target for the design parameters, and the resulting work products from the virtual system are quickly converted into the physical product. Models of the system are initially created at a high level of abstraction, and, through the model-based methodology, are driven to a full virtual implementation, then to an actual product.The model-based methodology approach proposes the use of an architecture exploration tool to facilitate the rapid exploration of various CPUs, memories, and peripherals (system architecture). The system architecture is shown in the upper right of Figure 2 . The upper left of Figure 2 shows early revisions of the functional models of the system, known as system behavior. The system behavior and system architecture are combined, and an optimal solution is achieved by iteratively comparing the performance of each partitioned alternative. The objective is to evaluate the various architectural and partitioning alternatives to gain a first order approximation of the optimum design.Some of the proposed EDA tools for architecture exploration offer the ability to model microcontroller architectures in only a few weeks duration. The simulations for architectural simulation may be only 80% accurate, but that is believed to be good enough to make the firstorder choices of microcontroller, timer architecture and memory usages. Our evaluations of the architectural exploration tools, however, indicate that the industry has not yet focused on solving microcontroller selection in a general way. As this paper presents, there is a tradeoff between simulation accuracy, cost of the modeling effort, and the time to model a new architecture. We are awaiting further tool maturation before expanding beyond paper evaluations of architecture exploration.The industry trend is toward building libraries of very accurate architecture models that execute the embedded software directly. A sufficient library of these detailed models can then be used to evaluate system architectures and also used for the final software development.We have focused our efforts on the lower left box of Figure 2; the highly accurate and fast simulation of a virtual system known as cycle-accurate simulation. This portion of the co-design market has matured to the point that it is now feasible to simulate a moderate sized ECU, such as an air-bag deployment module, at about 1/15th the speed of the actual hardware. As additional modɥls become available, these cycle-ࡡccurate simulations will be capable of solving much of the architectural exploration space as weŬl.DeŴailed anѤ highly accurate simulati䁯n encourages evaluation of thɥ system behavior onĠa proѰosed architecture. The models, as well as the target code, can be adapted to determine the optimum design solution. Full target software simulation is supported using a 32-bit CPU Virtual Processor Model (VPM), the microcontroller peripheral models, system ASIC models, and the environmental stimuli. The VPM is able to load and simulate the same executable image as used in traditional bench development. The models may be exported from CoMET to the lower cost METeor integrated development environment to provide a fixed platform (models cannot be changed) virtual product simulation.SIMULATION SPEED AND ACCURACYBefore we begin discussing the system, it is important to present some background material that highlights the levels of modeling abstraction and how they are best applied.In general, total simulation sࡡeࡡd decreasesРis detail is added to the model. Fuࡡctional models execute orders of magnitude faster than the m d els used during o nverification.The levels of abstraction used in product modeling include :Functional Simulation – Veࡡy little to no timing accuracy of the real hardware.Timed耠Functional Simulation – Contains estimated execution time of individual moduleࡡ.Cycle-Apprɯximate –䀠Timed fun t ional simulation techniques applied to instruction set and cycle accurate simulation.Instruction Set Simulation – Cross-compiled code executed on model of target CPU.Cycle-Accurate – Simulation is very similar (or identical) to hardware behavior.二、英文翻译硬件/软件的设计和开发过程埃弗瑞特-鲁普金和迈克-盖布里克Delphi公司电子和安全部门介绍半导体产业的生产过程和设计技术的进步，革新了汽车和消费电子产品。