6.2 8位乘法器的设计1.实验目的（1）熟悉isEXPERT/MAX+plusisEXPERT/MAX+plus II/Foudation Series 软件的基本使用方法。

（2）熟悉GW48-CK EDA实验开发系统的基本使用方法。

（3）学习VHDL基本逻辑电路的综合设计。

2．实验内容设计并调试好由8位加法器构成的以时序逻辑方式设计的8位乘法器。

此乘法器通过判断被乘数的位值为1还是零，并通过乘数的左移与上一次和相加的方法，实现了8位乘法的运算，并用GW48-CK EDA实验开发系统进行硬件验证。

3.实验条件（1）开发设备：Lattice ispEXPERT。

（2）实验设备：GW48-CK EDA实验开发系统。

（3）拟用芯片：ispLSI1032E PLCC-84或EPF10K10LC84-3或XCS05/XL PLCC84以及运算控制电路和外部时钟。

4.实验设计1）系统的原理框图2）VHDL源程序（1）选通与门模块的源程序ANDARITH.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ANDARITH ISPORT(ABIN: IN STD_LOGIC;DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT: OUT STD_LOGIC_vector(7 DOWNTO 0)); END ENTITY ANDARITH;ARCHITECTURE ART OF ANDARITH ISBEGINPROCESS(ABIN,DIN)ISBEGINFOR I IN 0 TO 7 LOOPDOUT(I)<=DIN(I)AND ABIN;END LOOP;END PROCESS;END ARCHITECTURE ART;(2)16位锁存器的源程序REG16B.VHD LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG16B ISPORT (CLK: IN STD_LOGIC;CLR: IN STD_LOGIC;D: IN STD_LOGIC_VECTOR(8 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ENTITY REG16B;ARCHITECTURE ART OF REG16B ISSIGNAL R16S: STD_LOGIC_VECTOR(15 DOWNTO 0); BEGINPROCESS(CLK,CLR)ISBEGINIF CLR='1' THEN R16S<="0000000000000000"; ELSIF CLK'EVENT AND CLK= '1' THENR16S(6 DOWNTO 0)<=R16S(7 DOWNTO 1);R16S(15 DOWNTO 7)<=D;END IF;END PROCESS;Q<=R16S;END ARCHITECTURE ART;(3)8位右移寄存器的源程序SREG8B.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SREG8B ISPORT(CLK:IN STD_LOGIC; LOAD:IN STD_LOGIC; DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB: OUT STD_LOGIC);END ENTITY SREG8B;ARCHITECTURE ART OF SREG8B ISSIGNAL REG8B :STD_LOGIC_VECTOR(7 DOWNTO 0); BEGINPROCESS(CLK, LOAD)ISBEGINIF CLK'EVENT AND CLK='1'THENIF LOAD='1'THEN REG8B<=DIN;ELSE REG8B(6 DOWNTO 0)<=REG8B(7 DOWNTO 1); END IF;END IF;END PROCESS;QB<=REG8B(0);END ARCHITECTURE ART;(4)乘法运算控制器的源程序ARICTL.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ARICTL ISPORT(CLK:IN STD_LOGIC; START:IN STD_LOGIC; ARIEND:OUT STD_LOGIC;CLKOUT: OUT STD_LOGIC;RSTALL: OUT STD_LOGIC);END ENTITY ARICTL;ARCHITECTURE ART OF ARICTL ISSIGNAL CNT4B: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINRSTALL<=START;PROCESS(CLK,START)ISBEGINIF START='1'THEN CNT4B<="0000";ELSIF CLK'EVENT AND CLK='1'THENIF CNT4B<8 THENCNT4B <=CNT4B+1;END IF;END IF;END PROCESS;PROCESS(CLK,CNT4B,START)ISBEGINIF START='0' THENIF CNT4B<8 THENCLKOUT <=CLK;ARIEND<='0';ELSE CLKOUT<='0';ARIEND<='1';END IF;ELSE CLKOUT<=CLK;ARIEND<='0';END IF;END PROCESS;END ARCHITECTURE ART;(5)8位乘法器的源程序MULTI8X8.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MULTI8X8 ISPORT(CLK:IN STD_LOGIC;START:IN STD_LOGIC;A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);ARIEND:OUT STD_LOGIC;DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ENTITY MULTI8X8;ARCHITECTURE ART OF MULTI8X8 ISCOMPONENT ARICTL ISPORT(CLK:IN STD_LOGIC;START:IN STD_LOGIC;CLKOUT:OUT STD_LOGIC; RSTALL:OUT STD_LOGIC; ARIEND: OUT STD_LOGIC);END COMPONENT ARICTL;COMPONENT ANDARITH ISPORT(ABIN:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT ANDARITH;COMPONENT ADDER8B ISPORT(CIN: IN STD_LOGIC;A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);S: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);COUT: OUT STD_LOGIC);END COMPONENT ADDER8B ;COMPONENT SREG8B ISPORT(CLK: IN STD_LOGIC;LOAD: IN STD_LOGIC;DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);QB: OUT STD_LOGIC);END COMPONENT SREG8B ;COMPONENT REG16B ISPORT (CLK: IN STD_LOGIC;CLR: IN STD_LOGIC;D: IN STD_LOGIC_VECTOR(8 DOWNTO 0);Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END COMPONENT REG16B ;SIGNAL S1: STD_LOGIC;SIGNAL S2: STD_LOGIC;SIGNAL S3: STD_LOGIC;SIGNAL S4: STD_LOGIC;SIGNAL S5: STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL S6: STD_LOGIC_VECTOR(8 DOWNTO 0);SIGNAL S7: STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINDOUT<=S7; S1<='0';U1:ARICTL PORT MAP(CLK=>CLK,START=>START,CLKOUT=>S2,RSTALL=>S3,ARIEND=>ARIEND);U2:SREG8B PORT MAP(CLK=>S2,LOAD=>S3,DIN=>A,QB=>S4);U3:ANDARITH PORT MAP(ABIN=>S4,DIN=>B,DOUT=>S5);U4:ADDER8B PORT MAP(CIN=>S1,A=>S7(15 DOWNTO 8)),B=>S5(7 DOWNTO 0),S=>S6(7 DOWNTO 0),COUT=>S6(8); U5:REG16B PORT MAP(CLK=>S2,CLR=>S3,D=>S6(8 DOWNTO 0),Q=>S7(7 DOWNTO 0));END ARCHITECTURE ART;5.系统仿真文件当ATRRT为高电平时，将16位寄存器清零，当START为低电平时，在CLK为1时进行乘法运算，通过8次移位和加法操作，运算进行8个CLK为1的时钟，之后得到输出结果，且ARIEND为1,乘法运算结束。