8
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4. Benefits
Cost saving !!
MERIT !!
* Chip price down : 10~20% ↓ * PCB cost saving : 4Layer -> 2Layer & Smaller Board * Stock management cost saving * SMD cost saving & High Productivity
8 Lead
Main User Nokia, SEC, LGE SEC, LGE, P&Q
SEC
BTEP-5L
2.2x6.1x0.85
BP31ABB, BP24AD etc
C1, C3 R1, R2 Built-in
Mass production available From 2010. Sep.
UTEP-6L 2.55x3.4x0.65Βιβλιοθήκη STEP-5L HTEP-8L
2.2x6.1x0.65 5x7x0.95
UP46B etc TP-22B etc IMD16N30, IMD18N30etc
Miniature
Mass production available From 2010. Sep.
Low Profile
For Smart Module
Protection One Chip
INTERSOLL CO., LTD
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1

Content
1. What is Protection One Chip? 2. Package Classification 3. Why Protection One Chip? 4. Benefits 5. DVP Road Map 6. Achievement & Goal 7. Certification 8. Major Customers
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7. Certification
<RS C 0101>
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<ISO9001>
13
<ISO14001>

Nokia Dell, HP,SEC,LGE
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2. Package Classification
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4. Benefits
Simple design !!
2 Chip
signal Pattern
POC
MERIT !!
The World Choose Intersoll’s Technology
2 Chip(Normal)
2 Chip(Small)
3.1 X 10.0
3.1 X 7.3
POC(TSSOP-8L)
7

4. Benefits
Reliability up !!
IC + FET
POC
B
V
B
V
+
+
+
+
VDD
DS
VDD
VSS
V-
VSS
V-
DO
CO
DO
CO
G1
G2
S1
S2
B-
S1
S2
V-
B-
S1
S2
V
-
MERIT !!
* Approved : NOKIA, SEC, SDI, LGE, LGC, SEMC, P&Curitel , etc * Using Reliable Materials * Minimize the damage from EMI, ESD(Minimize!!) * Stable control of electric signal from IC to FET
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1. What is Protection One Chip ?
Protection One Chip. It is designed “MOSFET” and “Protection IC” as One package.
The World Choose Intersoll’s Technology
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5. DVP Road Map – Product
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6. Achievement & Goal
3. Why Protection One Chip?
Cost Reduction
Stable Supply
CUSTOMER’S SATISFACTION
Simple Design
High Reliability
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→ eliminate 6~9 solder pins(2 Chip → 1Chip) → reduce failure ratio → reduce QC cost & time
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5. DVP Road Map – Protection One Chip Package
Device
Feature
TEP-5L 2.2x6.1x0.85 MP31ABB(I), MP24AD, LI506 etc Main PKG
TEP-6L 2.2x5.1x0.75
SP31ABE(F), SP24AD etc
Stack Type
TSSOP-8L 3x6.4x1.2
MP05AB, LI804 etc
Protection One Chip Structure
Parallel Die Type
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3
Stack Die Type

2. Package Classification
PKG
Size[cm]
POC(TEP-5L)
3.0 X 6.4
2.15 X 6.1
* Available device : C/Phone, MP3, B/Tooth * Simple pattern : 4 layer → 2 layer * shorten building time * Available space for PTC in PCB(Extra area) * Size reduction : can reduce max 4mm