外文资料翻译STC89C52 processi ng chipPrime features:With MCS - 51 SCM product compatibility, 8K bytes in the system programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number poin ter, power ide ntifier. Efficacy: characteristicsSTC89C52 is one kind of low power consumption, high CMOS8 bit micro-co ntroller, 8K in system programmable Flash memory. Use high-de nsity nonv olatile storage tech no logy, and in dustrial 80C51 product in structi on and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and on li ne system programmable Flash, in crease STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16 timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/c oun ters, serial, continu ous to work. Protectio n asa na patter n, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices.Mouth: P0 P0 mouth is a two-way ope n drain I/O. As export, each can drive eight TTL logic level. For P0 port to write "1", foot as the high impeda nee input.When access to exter nal programs and nu merical memory, also known aslow P0 mouth eight address/nu merical reuse. In this mode, with the in tern al P0 resistor.In the flash when programming, also used for P0 mouth; absorb in struct ion bytes In the process, the output comma nd byte calibrati on. When the program requires external, calibration on pull-up resistors.Mouth: P1 mouth P1 is an internal resistance of the eight two-way I/O buffers can drive, P1 output four TTL logic level. To write "1" P1 port, the internal resista nce to port, can push as in put mouth. Whe n used as in put, exter nal and in ternal foot because of low resista nce, will output curre nt (IIL).In addition, P1.0 and P1.2 respectively timer/counter 2 external counting in put (P1.0 / T2) and whe n the trigger editor/co un ter P1.1 in put (2), specificT2EX/are shown below. In programming and calibration, flash P1 mouth absorb eight address low byte.Efficacy: the foot.P1.0 T2 (timer/co un ter T2 external coun ti ng in put), clock outputP1.1 T2EX (timer/co un ter T2 capture/overloaded triggered sig nals and directi on con trol),P1.5 MOSI (with) on li ne system program ming,P1.6 MISO (with) on li ne system program ming,P1.7 SCK (with) on li ne system program ming,Mouth: P2 P2 mouth is an internal resista nce of the eight two-way I/O buffers and P2 output can drive four TTL logic level. To write "1" P2 port, the internal resista nce to port, can push as in put mouth. When used as in put, exter nal and in ternal foot because of low resista nce, will output curre nt (IIL).In the exter nal program memory access or use 16bit exter nal nu merical memory address read (for example MOVX execution DPTR @), P2 mouth send out high 8 address. In this application, P2 mouth on the internal use strong pull send 1. In using 8-bit address (such as MOVX @ Rl) access to external numerical memory, P2 mouth output P2 latches content. In programming and calibration, flash P2 mouth also absorb high eight address byte and some con trol sig nal.P3: a P3 mouth on the in side of the eight two-way pull-up resistors I/O buffers can drive, p2 output four TTL logic level. For P3 port to write "1", the internal resista nee to port, can push as in put mouth. Whe n used as in put, exter nal and in ternal foot because of low resista nee, will output curre nt (IIL).P3 mouth AT89S52 special fun cti ons (also as the sec ond efficacy), are show n below. In programming and calibration, flash also absorb some P3 mouth con trol sig nals.Port pin sec ond efficacy:P3.0 RXD (serial in put)P3.1 TXD (serial export),P3.2 INTO the disco ntin uous (0)P3.3 INT1 (1) the disco ntin uousP3.4 (time/ccounter TO 0)P3.5 T1 (1) time/cou nter,P3.6 WR (exter nal nu merical memory write for)P3.7 RD (exter nal nu merical memory read for)In addition, also absorb some used in mp3 mouth FLASH memory program ming and calibrati on of program con trol sig nals.RST, reset in put: whe n the vibrator, RST pin appeared two machi ne cycle above high level will be reset the chip.ALE/PROG - when access to external program memory or numerical memory, ALE (address latch allow) output pulses are used to latch address of low eight bytes. Normally, ALE with clock frequencies are 1/6 output pulse signal with fixed, so it can be used for the purpose or output clocks. Timing Those who want an attention is: whenever access to external numerical memory will skip a ALE pulse.For FLASH memory program ming, this pin is used for in put program ming pulse (.) PROGIf n ecessary, but through special effect to the zone registers (SFR) 8EH DO position, the unit can be banned ALE operations. This position is a bit, MOVX and MOVC instructions will be activated. ALE -- In addition, the foot will be weak,execute exter nal program MCU hig n should be bann ed, a void. Set ALE PSEN - program storage PSEN allowed (output is outside of the program memory read, choose com muni catio n by exter nal program memory whe n tak ing AT89C52 in structi ons (or), each mach ine cycle PSEN twice, two pulse output is useful, during this period, when access to external numerical memory, will skip PSEN twice.EA/VPP - exter nal access permissi on, to make the CPU on ly access to exter nal program memory (address for 0000H - FFFFH), EA end must rema in low level (ground). Should notice is: if a LB1 is encrypted, reset when program ming will latch EA end.As for the high level of the EA (VCCS), the CPU is the impleme ntati on of the program memory internal in structi ons.FLASH memory when programming, this pin plus + 12 v programming allow power Vpp, of course, that is the part is used to Vpp voltage 12V program ming.中文翻译STC89C52处理芯片首要性能：与MCS-51单片机产物兼容、8K字节在系统可编程Flash存储器、1000次擦写周期、全静态操作：0Hz〜33Hz、三级加密程序存储器、32个可编程I/O 口线、三个16位定时器/计数器八个间断源、全双职工UART 串行通道、低功耗空闲和掉电模式、掉电后间断可唤醒、看门狗定时器、双数值指针、掉电标识符。