大规模数字逻辑题目：流水灯控制专业电子信息科学与技术班级学号学生设计时间教师评分2013年12 月10 日目录一、概述 (1)二、设计目的 (1)三、设计容 (1)四、设计原理图 (2)五、引脚分配情况 (2)六、源程序代码 (2)VerilogHDL 程序： (2)分频器部分： (5)七、心得体会 (6)八、参考文献 (7)一、概述流水灯是一串按一定的规律像流水一样连续闪亮，流水灯控制是可编程控制器的一个应用，其控制思想在工业控制技术领域也同样适用。
流水灯控制可用多种方法实现，但对现代可编程控制器而言，基于EDA技术的流水灯设计也是很普遍的。
二、设计目的1、熟悉利用Quartus II 开发数字电路的基本流程和Quartus II 软件的相关操作。
2、掌握基本的设计思路，软件环境参数配置，仿真，管脚分配，利用JTAG/AS 进行下载等基本操作。
3、了解VerilogHDL 语言设计或原理图设计方法。
4、通过本此设计，了解流水灯的工作原理，掌握其逻辑功能及设计方法。
三、设计容1、用VerilogHDL语言设计一个流水灯，输入0的时候led~led7，1Hz正向流水3次，然后全亮；然后2Hz逆向流水5次全亮；循环。
输入1的时候led0~led7,0.5Hz奇数流水2次，全亮，1Hz偶数流水4次，全亮，然后循环。
2、用QuartusII 软件进行编译，仿真，下载到实验平台进行验证。
四、设计原理图en为可调输入，输出为8位数据，为流水灯实验，试用8个LED指示灯来表示，具体引脚分配见下。
五、引脚分配情况六、源程序代码VerilogHDL 程序：module LED( clk,led,en );input clk;input en;output [7:0]led;// 输出端口定义为寄存器型reg [7:0] led;reg [8:0] state1;reg [8:0] state2;always (posedge clk )// always语句，表示每当CLK的上升沿到来时，完成begin-end 之间语句的操作if(!en)begin state2 = 0;state1 = state1 + 1; // one clk,one statecase(state1)1,2: led <= 8'b00000001; //1-7 zhengxu,3bian3,4: led <= 8'b00000010;5,6: led <= 8'b00000100;7,8: led <= 8'b00001000;9,10: led <= 8'b00010000;11,12: led <= 8'b00100000;13,14: led <= 8'b01000000;15,16: led <= 8'b10000000;17,18: led <= 8'b00000001;19,20: led <= 8'b00000010;21,22: led <= 8'b00000100;23,24: led <= 8'b00001000;25,26: led <= 8'b00010000;27,28: led <= 8'b00100000;29,30: led <= 8'b01000000;31,32: led <= 8'b10000000;33,34: led <= 8'b00000001;35,36: led <= 8'b00000010;37,38: led <= 8'b00000100;39,40: led <= 8'b00001000;41,42: led <= 8'b00010000;43,44: led <= 8'b00100000;45,46: led <= 8'b01000000;47,48: led <= 8'b10000000;49: led <= 8'b11111111; //quanliang50: led <= 8'b10000000;51: led <= 8'b01000000;52: led <= 8'b00100000;53: led <= 8'b00010000;54: led <= 8'b00001000;55: led <= 8'b00000100;56: led <= 8'b00000010;57: led <= 8'b00000001;58: led <= 8'b10000000;59: led <= 8'b01000000;60: led <= 8'b00100000;61: led <= 8'b00010000;62: led <= 8'b00001000;63: led <= 8'b00000100;64: led <= 8'b00000010;65: led <= 8'b00000001;66: led <= 8'b10000000;67: led <= 8'b01000000;68: led <= 8'b00100000;69: led <= 8'b00010000;70: led <= 8'b00001000;71: led <= 8'b00000100;72: led <= 8'b00000010;73: led <= 8'b00000001;74: led <= 8'b10000000;75: led <= 8'b01000000;76: led <= 8'b00100000;77: led <= 8'b00010000;78: led <= 8'b00001000;79: led <= 8'b00000100;80: led <= 8'b00000010;81: led <= 8'b00000001;82: led <= 8'b10000000;83: led <= 8'b01000000;84: led <= 8'b00100000;85: led <= 8'b00010000;86: led <= 8'b00001000;87: led <= 8'b00000100;88: led <= 8'b00000010;89: led <= 8'b00000001;90: led <= 8'b11111111;91: begin led <= 8'b00000000;state1=0;enddefault: state1 = 0;endcaseendelsebegin state1 = 0;state2 = state2 + 1; // one clk,one statecase(state2)1,2,3,4: led <= 8'b00000001;5,6,7,8: led <= 8'b00000100;9,10,11,12: led <= 8'b00010000;13,14,15,16: led <= 8'b01000000;17,18,19,20: led <= 8'b00000001;21,22,23,24: led <= 8'b00000100;25,26,27,28: led <= 8'b00010000;29,30,31,32: led <= 8'b01000000;33: led <= 8'b11111111;34,35: led <= 8'b00000010;36,37: led <= 8'b00001000;38,39: led <= 8'b00100000;40,41: led <= 8'b10000000;42,43: led <= 8'b00000010;44,45: led <= 8'b00001000;46,47: led <= 8'b00100000;48,49: led <= 8'b10000000;50,51: led <= 8'b00000010;52,53: led <= 8'b00001000;54,55: led <= 8'b00100000;56,57: led <= 8'b10000000;58,59: led <= 8'b00000010;60,61: led <= 8'b00001000;62,63: led <= 8'b00100000;64,65: led <= 8'b10000000;66: led <= 8'b11111111;67:begin led <= 8'b00000000;state2=0;enddefault: state2 = 0; // default,8'b11111110endcaseendEndmodule分频器部分：module clk_div(clk_out,clk_in);input clk_in;output clk_out;reg clk_out;reg[25:0] counter; //50_000_000=1011_1110_1011_1100_0010_0000_00parametert=25_000_000; /// 50MHz is the sys clk,50_000_000=2FAF080 always (posedge clk_in)begincounter<=counter+1;if(counter==cnt/2-1)beginclk_out<=!clk_out;counter<=0;endendendmodule七、心得体会通过这次课程设计，我拓宽了知识面，锻炼了能力，综合素质得到较大提高。