实验十七数字时钟实验目的设计一个可以计时的数字时钟，其显示时间范围是00:00:00~23:59:59，且该时钟具有暂停计时、清零等功能。
实验器材1、SOPC实验箱2、计算机（装有Quartus II 7.0软件）实验预习1、了解时钟设计原理和各主要模块的设计方法。
2、提前预习，编写好主模块的VHDL程序。
实验原理数字时钟框图如图17.1所示，一个完整的时钟应由4部分组成：秒脉冲发生电路、计数部分、译码显示部分和时钟调整部分。
1、秒脉冲发生：一个时钟的准确与否主要取决秒脉冲的精确度。
可以设计分频电路对系统时钟50MHz进行50000000分频从而得到稳定的1Hz基准信号。
定义一个50000000进制的计数器，将系统时钟作为时钟输入引脚clk，进位输出即为分频后的1Hz信号。
2、计数部分：应设计1个60进制秒计数器、1个60进制分计数器、1个24进制时计数器用于计时。
秒计数器应定义clk（时钟输入）、rst（复位）两个输入引脚，Q3~Q0（秒位）、Q7~Q4（十秒位）、Co（进位位）9个输出引脚。
分、时计数器类似。
如需要设置时间可再增加置数控制引脚Set和置数输入引脚d0~d7。
3、译码显示部分：此模块应定义控制时钟输入、时分秒计数数据输入共25个输入引脚；8位显示码输出（XQ7~XQ0）、6位数码管选通信号（DIG0~DIG5）共14个输出引脚。
在时钟信号的控制下轮流选择对十时、时、十分、分、十秒、秒输入信号进行译码输出至XQ7~XQ0，并通过DIG0~DIG5输出相应的选通信号选择数码管。
每位显示时间控制在1ms 左右。
时钟信号可由分频电路引出。
4、各模块连接方式如图17.1所示。
图17.1 数字时钟框图系统时钟为1024Hz产生1Hz模块Library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;Entity clk_1Hz ISPORT(sys_clk:in std_logic;clk_1Hz:out std_logic);END entity clk_1Hz;Architecture bhv of clk_1Hz ISsignal clk_1Hz_r:std_logic;signal count:std_logic_vector(9 downto 0); BeginProcess(sys_clk)BeginIF sys_clk'EVENT AND sys_clk='1' THEN IF count="1000000000" THENcount<=(others=>'0');clk_1Hz_r<=NOT clk_1Hz_r;ELSE count<=count+1;END IF;END IF;END Process;clk_1Hz<=clk_1Hz_r;END bhv;24进制模块Library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;Entity counter24 ISPORT(clk,rst:in std_logic;bcd:out std_logic_vector(7 downto 0);up:out std_logic);END entity counter24;Architecture bhv of counter24 ISsignal bcd_r:std_logic_vector(7 downto 0); signal up_r:std_logic;BeginProcess(clk,rst)BeginIF rst='0' THENbcd_r<=(others=>'0');up_r<='0';ELSIF clk'EVENT AND clk='1' THENIF bcd_r="00100100" THENbcd_r<=(others=>'0');up_r<='1';ELSIF bcd_r(3 downto 0)="1001" THENbcd_r(3 downto 0)<="0000";bcd_r(7 downto 4)<=bcd_r(7 downto 4)+1;up_r<='0';ELSE bcd_r(3 downto 0)<=bcd_r(3 downto 0)+1;up_r<='0';END IF;END IF;END PROCESS;bcd<=bcd_r;up<=up_r;END bhv;60进制模块Library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;Entity counter60 ISPORT(clk,rst:in std_logic;bcd:out std_logic_vector(7 downto 0);up:out std_logic);END entity counter60;Architecture bhv of counter60 ISsignal bcd_r:std_logic_vector(7 downto 0);signal up_r:std_logic;BeginProcess(clk,rst)BeginIF rst='0' THENbcd_r<=(others=>'0');up_r<='0';ELSIF clk'EVENT AND clk='1' THENIF bcd_r="01011001" THENbcd_r<=(others=>'0');up_r<='1';ELSIF bcd_r(3 downto 0)="1001" THENbcd_r(3 downto 0)<="0000";bcd_r(7 downto 4)<=bcd_r(7 downto 4)+1;up_r<='0';ELSE bcd_r(3 downto 0)<=bcd_r(3 downto 0)+1;up_r<='0';END IF;END IF;END PROCESS;bcd<=bcd_r;up<=up_r;END bhv;数码管译码显示模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_Arith.ALL;USE IEEE.STD_LOGIC_Unsigned.ALL;ENTITY xianshi ISPORT(clk:IN STD_LOGIC;datain:IN STD_LOGIC_VECTOR(31 DOWNTO 0);dig,seg:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END ENTITY;ARCHITECTURE one OF xianshi ISSIGNAL counter: std_logic_vector(2 DOWNTO 0); SIGNAL display: std_logic_vector(3 DOWNTO 0); SIGNAL seg_r: std_logic_vector(7 DOWNTO 0); SIGNAL dig_r: std_logic_vector(7 DOWNTO 0);BEGINAAA:PROCESS(clk)BEGINIF clk'EVENT AND clk='1' THENcounter<=counter+1;END IF;END PROCESS AAA;BBB:PROCESS(counter)BEGINCASE counter ISWHEN "000" => dig_r<="01111111";WHEN "001" => dig_r<="10111111";WHEN "010" => dig_r<="11011111";WHEN "011" => dig_r<="11101111";WHEN "100" => dig_r<="11110111";WHEN "101" => dig_r<="11111011";WHEN "110" => dig_r<="11111101";WHEN "111" => dig_r<="11111110";WHEN OTHERS =>NULL;END CASE;END PROCESS BBB;CCC:PROCESS(counter,datain)BEGINCASE counter ISWHEN "000" => display<=datain(31 DOWNTO 28);WHEN "001" => display<=datain(27 DOWNTO 24);WHEN "010" => display<=X"a";WHEN "011" => display<=datain(19 DOWNTO 16);WHEN "100" => display<=datain(15 DOWNTO 12);WHEN "101" => display<=X"a";WHEN "110" => display<=datain(7 DOWNTO 4);WHEN "111" => display<=datain(3 DOWNTO 0);WHEN OTHERS =>NULL;END CASE;END PROCESS CCC;DDD:PROCESS(display)BEGINCASE display ISWHEN X"0"=> seg_r<=X"c0";WHEN X"1"=> seg_r<=X"f9";WHEN X"2"=> seg_r<=X"a4";WHEN X"3"=> seg_r<=X"b0";WHEN X"4"=> seg_r<=X"99";WHEN X"5"=> seg_r<=X"92";WHEN X"6"=> seg_r<=X"82";WHEN X"7"=> seg_r<=X"f8";WHEN X"8"=> seg_r<=X"80";WHEN X"9"=> seg_r<=X"90";WHEN X"a"=> seg_r<=X"BF"; --显示‘-’WHEN X"b"=> seg_r<=X"83";WHEN X"c"=> seg_r<=X"c6";WHEN X"d"=> seg_r<=X"a1";WHEN X"e"=> seg_r<=X"86";WHEN X"f"=> seg_r<=X"8e";WHEN OTHERS =>NULL;END CASE;END PROCESS DDD;seg<=seg_r;dig<=dig_r;END ARCHITECTURE; 原理图。