专业：计算机科学与技术班级：CS1409学号：U**********名：***电话：158****5005邮件：*****************完成日期：2016.6.13 2016Verilog 语言·实验报告·计算机科学与技术学院目录1数据通路实验 (1)1.1实验目的 (1)1.2实验内容及要求 (1)1.3实验方案 (2)1.4实验步骤 (2)1.5故障及分析 (2)1.6仿真与结果 (3)1.7心得与体会 (4)2FSM实验 (5)2.1实验目的 (5)2.2实验内容及要求 (5)2.3实验方案 (6)2.4实验步骤 (6)2.5故障及分析 (7)2.6仿真与结果 (7)2.7心得与体会 (8)3意见和建议 (9)4附录 (10)1 数据通路实验1.1 实验目的综合应用掌握的简单组合电路和时序电路的设计方法，完成一个简单的数据通路的设计。

1.2 实验内容及要求1. 根据下图给出的数据通路（图中R0、R1和ACC是寄存器，+是加法器，其它则是多路选择器），完成相应的Verilog程序设计，图中数据线的宽度为8位，要求可以扩充至16位或者是32位；2. 根据下图给出的数据通路（图中SUM和NEXT是寄存器，Memory是存储器，+是加法器，==0是比较器，其它则是多路选择器），完成相应的Verilog程序设计，图中数据线的宽度为8位，要求可以扩充至16位或者是32位。

实验要求：程序必须自己编写，满足数据通路设计要求，综合结果正确。

1.3 实验方案根据要求，先把选择器、加法器、寄存器、比较器和存储器分模块编写，在主模块中根据数据通路调用即可。

题目中要求数据线宽度为8位，并且可以扩充至16位或32位，所以在前面定义WIDTH，利用parameter的参数传递功能来实现。

1.4 实验步骤1.分模块编写代码（见附录）2.运行综合Run Synthesis3.综合成功后检查RTL Analysis中的电路图Schematic1.5 故障及分析刚开始跑出来很多线是断的，后来发现是引脚对应部分的代码没有写完整。

后来加法器和ACC的参数顺序写错，导致接线与题给的不一致，发现问题后及时改正了。

1.6 仿真与结果Schematic图形如下：第一个数据通路：第二个数据通路：由以上两图可得，成功完成了要求的数据通路的设计，满足了各基本器件的输入输出链接要求；改变数据线宽度后再检查电路图，发现数据线做出相应改变，完成该实验。

1.7 心得与体会对数据通路的设计有了更好的理解，明白了数据通路的基本器件构成，熟悉了这些器件的功能和端口，掌握了Verilog完成基本运算器件的设计，完成了数据通路的设计。

2 FSM实验2.1 实验目的掌握用Verilog语言进行FSM设计、实现和仿真的方法。

2.2 实验内容及要求5.1_1、用FSM实现一个mealy型序列检测器，对一位的串行输入序列中的“1”的数量进行检测。

如果“1”的总数可以被3整除，输出“1”，否则输出“0”。

5.1_2、用FSM实现一个moore型序列检测器，对两位的串行输入序列进行检测。

输入01,00时，输出0，输入11,00时，输出1，输入10,00时，输出反向。

5.1_3、用FSM实现一个计数器（采用存储器），对一位的输入进行计数。

计数序列为：000,001,011，101,111，010。

5.2、用FSM实现一个序列识别器，该FSM的状态转移图如下所示，它能够对一位的串行输入序列中的“1”的数量进行检测。

如果FSM发现输入“1”的总数可以被3整除时，输出“1”；否则，输出“0”。

同时针对“***********”输入序列，写出相应的仿真程序并进行真波测试。

2.3 实验方案先根据要求画出状态图，根据状态图编写程序，根据程序编写仿真程序，最后得出结果和结论。

2.4 实验步骤5.1_1状态图：in=1/0in=0/0in=1/0 in=1/0in=1/15.1_2状态图：in=00in=01 in=10 in=11in=00 in=00 in=00out=0 out 翻转 out=1S0 S1S4 S3S0S1 S2S3S4 S5 S65.1_3状态图：1.根据以上状态图编写源程序（见附录）2.运行综合Run Synthesis3.综合正确后编写仿真程序4.仿真，得到仿真波形，验证结果2.5 故障及分析无故障2.6 仿真与结果5.1_1：如图，1的个数是3的倍数时输出1与预期一致5.1_2：如图，输入01后再输入00，输出0；输入11后再输入00，输出1；输入10后再输入00，输出翻转：与预期一致5.1_3：如图，输出序列为000,001,011,101,111,010（重复）与预期一致5.2：如图，1的个数是3的倍数时输出1与预期一致2.7 心得与体会这次实验通过FSM设计明白了设计的过程和步骤，首先要知道分为哪些状态，设计的是何种电路，如何选择用mealy还是moore型电路，状态转移要如何实现。

知道了mealy型和moore型电路的区别：当要求输出对输入快速响应并希望电路简单时选择mealy型，当要求时序输出稳定，能接受输出序列晚一个周期，即选择moore型电路不增加电路复杂性时，选择moore型电路。

3 意见和建议建议老师上课还是用中文PPT比较好，另外作业练习也用中文给出来，题目要求也尽量具体些，这样会减少我们学习的成本，更加有效的学习这门课。

4 附录源程序：4.1（第一个数据通路）//主模块module text4(S0,S1,S2,S3,Clk,reset,load,outR0,outR1,outACC,outS0,outS1,outS2,outS3,outA); parameter WIDTH=8; //位宽8位input S0,S1,S2,S3,Clk,reset,load;output [WIDTH-1:0] outR0,outR1,outACC,outS0,outS1,outS2,outS3,outA;register #(8) R0(inR0,Clk,reset,load,outR0);register #(8) R1(inR1,Clk,reset,load,outR1);register #(8) ACC(inACC,Clk,reset,load,outACC);mux #(8) S0(S0,inS00,inS01,outS0);mux #(8) S1(S1,inS10,inS11,outS1);mux #(8) S2(S2,inS20,inS21,outS2);mux #(8) S3(S3,inS30,inS31,outS3);add #(8) W1(inA0,inA1,outA);assign inS00=outS3;assign inS10=outS3;assign inS01=outR0;assign inS20=outR0;assign inS11=outR1;assign inS21=outR1;assign inA0=outACC;assign inS31=outACC;assign inACC=outA;assign inA1=outS2;assign inS30=outS2;assign inR1=outS1;assign inR0=outS0; endmodule//加法器模块module add(A,B,C);parameter WIDTH=8;input [WIDTH-1:0] A, B; output [WIDTH-1:0] C;wire [WIDTH:0] DA TA; assign DATA=A+B;assign C=DATA[7:0]; endmodule//寄存器模块module register(D,Clk,reset,load,Q); parameter WIDTH=8;input [WIDTH-1:0] D;input Clk,reset,load;output reg [WIDTH-1:0] Q; always @(posedge Clk)if (reset)beginQ <= 8'b0;end else if (load)beginQ <= D;endendmodule//二路选择器模块module mux(s,x,y,m);parameter WIDTH=8;input [WIDTH-1:0] x,y;input s;output [WIDTH-1:0] m;assign m =(s?y:x);endmodule4.2（第二个数据通路）//主模块moduletext2(SUM_SEL,NEXT_SEL,A_SEL,LD_SUM,LD_NEXT,NEXT_ZERO,outSUM_SEL,outNEXT_SE L,outA_SEL,outSUM,outNEXT,outA1,outA2,outMEM);parameter WIDTH=8;input SUM_SEL,NEXT_SEL,A_SEL,LD_SUM,LD_NEXT;wire [WIDTH-1:0]inSUM_SEL00,inSUM_SEL01,outSUM_SEL,inNEXT_SEL00,inNEXT_SEL01,outNEXT_SEL;output [WIDTH-1:0]outSUM_SEL,outNEXT_SEL,outA_SEL,outSUM,outNEXT,outA1,outA2,outMEM;output NEXT_ZERO;mux #(WIDTH) SUM_SEL(SUM_SEL,inSUM_SEL00,inSUM_SEL01,outSUM_SEL);mux #(WIDTH) NEXT_SEL(NEXT_SEL,inNEXT_SEL00,inNEXT_SEL01,outNEXT_SEL);mux #(WIDTH) A_SEL(A_SEL,inA_SEL00,inA_SEL01,outA_SEL);register #(WIDTH) SUM(inSUM,Clk,reset,LD_SUM,outSUM);register #(WIDTH) NEXT(inNEXT,Clk,reset,LD_NEXT,outNEXT);add #(WIDTH) A1(inA10,inA11,outA1);add #(WIDTH) A2(inA20,inA21,outA2);ROM #(WIDTH,WIDTH) MEM(outMEM,inMEM);COM #(WIDTH) COM(inCOM0,inCOM1,NEXT_ZERO); assign inA10=outSUM;assign inA11=outMEM;assign inNEXT_SEL00=outMEM;assign inNEXT_SEL01=0;assign inSUM_SEL00=outA1;assign inSUM_SEL01=0;assign inSUM=outSUM_SEL;assign inNEXT=outNEXT_SEL;assign inA20=outNEXT;assign inA21=1;assign inA_SEL00=outNEXT;assign inA_SEL01=outA2;assign inMEM=outA_SEL;assign inCOM0=outNEXT_SEL;assign inCOM1=0;endmodulemodule COM(a,b,out);parameter WIDTH=8;input [WIDTH-1:0] a,b;output out;reg out;always @(a or b)beginif(a>b)out=1;else out=0;endendmodule//存储器模块module ROM(ROM_data, ROM_addr);parameter data_WIDTH=8;parameter addr_WIDTH=8;output [addr_WIDTH-1:0] ROM_data;input [addr_WIDTH-1:0] ROM_addr;reg [addr_WIDTH-1:0] ROM [data_WIDTH-1:0]; // defining 4x2 ROMassign ROM_data = ROM[ROM_addr]; // reading ROM content at the address ROM_addr initial $readmemb ("ROM_data.txt", ROM, 0, 3); // load ROM content from ROM_data.txt file endmodule//寄存器模块module register(D,Clk,reset,load,Q);parameter WIDTH=8;input [WIDTH-1:0] D;input Clk,reset,load;output reg [WIDTH-1:0] Q;always @(posedge Clk)if (reset)beginQ <= 8'b0;end else if (load)beginQ <= D;endendmodule//加法器模块module add(A,B,C);parameter WIDTH=8;input [WIDTH-1:0] A, B;output [WIDTH-1:0] C;wire [WIDTH:0] DA TA;assign DATA=A+B;assign C=DATA[7:0];endmodule//二路选择器模块module mux(s,x,y,m);parameter WIDTH=8;input [WIDTH-1:0] x,y;input s;output [WIDTH-1:0] m;assign m =(s?y:x);endmodule5.1_1module lab5_1_1(input clk, input reset, input ain, output reg yout, output reg [3:0] count);reg [1:0] state, nextstate;parameter S0=0, S1=1, S2=2, S3=3;always @(posedge clk) // always block to update stateif (reset) beginstate <= S0;count = 0;endelsestate <= nextstate;always @(state or ain) // always block to compute output beginyout = 0;case(state)S0: if(!ain)yout = 1;S1: yout = 0;S2: yout = 0;S3: if(ain)yout = 1;endcaseendalways @(posedge clk) // always block to compute output beginif(ain)count = count + 1;endalways @(state or ain) // always block to compute nextstate begincase(state)S0: if(ain)nextstate = S1;else nextstate = S0;S1: if(ain)nextstate = S2;else nextstate = S1;S2: if(ain)nextstate = S3;else nextstate = S2;S3: if(ain)nextstate = S1;else nextstate = S3;endcaseendendmodule仿真程序：module lab5_1_1_tb();reg clk,reset,ain;wire yout;wire [3:0] count;integer i;parameter TIME = 400;parameter DELAY = 5;lab5_1_1 DUT (.clk(clk), .ain(ain), .count(count), .reset(reset), .yout(yout));initial begin#TIME $finish;endinitial beginclk = 0;for(i = 0; i < (TIME/DELAY); i = i + 1)#DELAY clk = ~clk;endinitial beginreset = 1;#(4*DELAY) reset = 0;#(34*DELAY) reset = 1;#(2*DELAY) reset = 0;endinitial beginain = 0;#(8*DELAY) ain = ~ain;#(4*DELAY) ain = ~ain;#(12*DELAY) ain = ~ain;#(8*DELAY) ain = ~ain;#(4*DELAY) ain = ~ain;#(6*DELAY) ain = ~ain;#(6*DELAY) ain = ~ain;endendmodule5.1_2module lab5_1_2(input clk, input reset, input [1:0] x, output reg yout, output reg [2:0] nextstate);reg [2:0] state;parameter S0=0, S11=1, S21=2, S31=3, S12=4, S22=5, S32=6;always @(posedge clk) // always block to update stateif (reset) beginstate <= S0;nextstate = S0;yout = 0;endelsestate <= nextstate;always @(state) // always block to compute output begincase(state)S0: yout = yout;S12: yout = 0;S22: yout = 1;S32: yout = ~yout;endcaseendalways @(state or x) // always block to compute nextstate begincase(state)S0: if(x == 1)nextstate = S11;else if(x == 3)nextstate = S21;else if(x == 2)nextstate = S31;S11: if(x == 0) nextstate = S12;else if(x == 1) nextstate = S11;else if(x == 3) nextstate = S21;else if(x == 2) nextstate = S31;S12: if(x == 1) nextstate = S11;else if(x == 3) nextstate = S21;else if(x == 2) nextstate = S31;S21: if(x == 0) nextstate = S22;else if(x == 1) nextstate = S11;else if(x == 3) nextstate = S21;else if(x == 2) nextstate = S31;S22: if(x == 1) nextstate = S11;else if(x == 3) nextstate = S21;else if(x == 2) nextstate = S31;S31: if(x == 0) nextstate = S32;else if(x == 1) nextstate = S11;else if(x == 3) nextstate = S21;else if(x == 2) nextstate = S31;S32: if(x == 1) nextstate = S11;else if(x == 3) nextstate = S21;else if(x == 2) nextstate = S31;endcaseendendmodule仿真程序：module lab5_1_2_tb();reg clk,reset;reg [1:0] x;wire [2:0] nextstate;wire yout;integer i;parameter TIME = 200;parameter DELAY = 5;lab5_1_2 DUT (.clk(clk), .x(x), .reset(reset), .yout(yout), .nextstate(nextstate));initial begin#TIME $finish;endinitial beginclk = 0;for(i = 0; i < (TIME/DELAY); i = i + 1)#DELAY clk = ~clk;endinitial beginreset = 1;#(4*DELAY) reset = 0;endinitial beginx = 0;#(8*DELAY) x = 3;#(2*DELAY) x = 2;#(2*DELAY) x = 0;#(4*DELAY) x = 2;#(2*DELAY) x = 0;#(2*DELAY) x = 3;#(2*DELAY) x = 0;#(2*DELAY) x = 1;#(2*DELAY) x = 0;#(2*DELAY) x = 2;#(2*DELAY) x = 3;#(2*DELAY) x = 0;#(6*DELAY) x = 2;#(6*DELAY) x = 0;endendmodule5.1_3module lab5_1_3(input clk, input reset, input x, output reg [2:0] yout, output reg [2:0] nextstate);reg [2:0] state;parameter S0=0, S1=1, S2=2, S3=3, S4=4, S5=5;always @(posedge clk) // always block to update stateif (reset) beginstate <= S0;nextstate = S0;endelsestate <= nextstate;always @(state or x) // always block to compute outputbegincase(state)S0: yout = 0;S1: yout = 1;S2: yout = 3;S3: yout = 5;S4: yout = 7;S5: yout = 2;endcaseendalways @(x or state) // always block to compute nextstate begincase(state)S0: if(x)nextstate = S1;else nextstate = S0;S1: if(x)nextstate = S2;else nextstate = S1;S2: if(x)nextstate = S3;else nextstate = S2;S3: if(x)nextstate = S4;else nextstate = S3;S4: if(x)nextstate = S5;else nextstate = S4;S5: if(x)nextstate = S0;else nextstate = S5;endcaseendendmodule仿真程序：module lab5_1_3_tb();reg clk,reset;reg x;wire [2:0] nextstate;wire [2:0] yout;integer i;parameter TIME = 400;parameter DELAY = 5;lab5_1_3 DUT (.clk(clk), .x(x), .reset(reset), .yout(yout), .nextstate(nextstate));initial begin#TIME $finish;endinitial beginclk = 0;for(i = 0; i < (TIME/DELAY); i = i + 1)#DELAY clk = ~clk;endinitial beginreset = 1;#(4*DELAY) reset = 0;endinitial beginx = 0;#(8*DELAY) x = 1;#(2*DELAY) x = 1;#(2*DELAY) x = 0;#(2*DELAY) x = 1;#(2*DELAY) x = 0;#(2*DELAY) x = 1;#(2*DELAY) x = 0;#(2*DELAY) x = 1;#(2*DELAY) x = 0;#(2*DELAY) x = 1;#(2*DELAY) x = 1;#(2*DELAY) x = 0;#(2*DELAY) x = 1;#(2*DELAY) x = 0;#(2*DELAY) x = 1;#(2*DELAY) x = 0;#(2*DELAY) x = 1;#(2*DELAY) x = 0;endendmodule5.2module lab5_2_1(input clk, input reset, input ain, output reg yout, output reg [3:0] count);reg [1:0] state, nextstate;parameter S0=0, S1=1, S2=2, S3=3;always @(posedge clk) // always block to update stateif (reset) beginstate <= S0;count = 0;endelse beginstate <= nextstate;if(ain)count = count + 1;endalways @(state) // always block to compute outputbeginyout = 0;case(state)S0: yout = 0;S1: yout = 0;S2: yout = 0;S3: yout = 1;endcaseendalways @(posedge clk) // always block to compute output beginendalways @(state or ain) // always block to compute nextstate begincase(state)S0: if(ain)nextstate = S1;else nextstate = S0;S1: if(ain)nextstate = S2;else nextstate = S1;S2: if(ain)nextstate = S3;else nextstate = S2;S3: if(ain)nextstate = S1;else nextstate = S3;endcaseendendmodule仿真程序:module lab5_2_1_tb();reg clk,reset,ain;wire yout;wire [3:0] count;integer i;parameter TIME = 400;parameter DELAY = 5;lab5_2_1 DUT (.clk(clk), .ain(ain), .count(count), .reset(reset), .yout(yout));initial begin#TIME $finish;endinitial beginclk = 0;for(i = 0; i < (TIME/DELAY); i = i + 1)#DELAY clk = ~clk;endinitial beginreset = 1;#(4*DELAY) reset = 0;#(34*DELAY) reset = 1;#(2*DELAY) reset = 0;endinitial beginain = 0;#(8*DELAY) ain = ~ain;#(4*DELAY) ain = ~ain;#(12*DELAY) ain = ~ain;#(8*DELAY) ain = ~ain;#(4*DELAY) ain = ~ain;#(6*DELAY) ain = ~ain;#(6*DELAY) ain = ~ain;endendmodul·指导教师评定意见·一、原创性声明本人郑重声明本报告内容，是由作者本人独立完成的。