佛山职业技术学院2013年07月1日洗衣机控制器的设计一、实训课题：洗衣机控制器的设计二、设计的内容及要求：1．设计一个洗衣机控制器，要求为：1)洗衣机控制器可以驱动洗衣机进行洗涤、漂洗或烘干；2)洗衣机控制器可以设置洗衣机的工作时间，工作时间最短1分钟，最长1小时，在工作过程中，工作时间以倒计时显示，若时间为0洗衣机停止工作；3)洗衣机在待机状态时，洗衣机控制器可以设置洗衣机的工作方式和工作时间；4)可以暂停或停止洗衣机工作；5)利用三个数码管显示洗衣机待机时的设置时间和工作时的运行时间，利用一位数码管显示洗衣机待机时所设置的工作方式运行时的工作方式；6）利用三个LED分别表示驱动洗衣机进行洗涤、漂洗或烘干。

7)洗涤时，电机中速正转；漂洗时，电机慢速反转；烘干时，电机快速正转。

2．洗衣机控制器可以划分为状态机模块、计时器模块、设置模块和显示选择模块。

在QuartusII中输入各个模块的代码，编译综合，仿真，完成各个模块的软件设计；3．把各个模块组合起来，综合编译，仿真，完成整个控制器系统的软件设计；4.选择电路方案锁定管脚，把程序下载到实验箱中，利用实验箱进行硬件实现；5.以EPM240为核心，设计洗衣机控制器硬件电路原理图和PCB版图。

6.完成实训报告。

实训报告包括：1)设计的任务和要求；2)模块的划分和系统总框图；3)各个模块的实现，包括模块的作用，模块的输入与输出情况，模块状态图，模块的代码以及注释，模块的波形图；4)系统的实现，包括系统总原理图，系统的波形图；5)管脚的锁定关系；6)电路原理图和PCB版图；7）实训总结。

三．设计思路：1）状态切换→有限状态机2）按定时时间及时→定时计数器3）显示时间→数码管译码驱动器4）接收设置时间→时间设置键盘扫描器5）接收设置模式→模式设置键盘扫描器6）切换显示运行时间和设置时间→二路选择器7）切换显示运行模式和设置模式→二路选择器8）控制电机→电机驱动器基本原理洗衣机控制器的设计主要是定时器的设计。

由一片FPGA和外围电路构成了电器控制部分。

FPGA接收键盘的控制命令，控制洗衣机的进水、排水、水位和洗衣机的工作状态、并控制显示工作状态以及设定直流电机速度、正反转控制、制动控制、起停控制和运动状态控制。

对芯片的编程采用模块化的VHDL(硬件描述语言)进行设计，设计分为三层实现，顶层实现整个芯片的功能。

顶层和中间层多数是由VHDL的元件例化语句实现。

中间层由无刷直流电机控制、运行模式选择、洗涤模式选择、定时器、显示控制、键盘扫描、水位控制以及对直流电机控制板进行速度设定、正反转控制、启停控制等模块组成，它们分别调用底层模块。

洗衣机控制器要完成的功能：1）控制四个功能状态切换：待机、洗涤、漂洗和干衣；2）按定时时间进行计时；3）显示时间或显示设置的时间；4）接收和保存设置的时间；5）能接收模式输入；6）能显示设置模式和当前工作模式；7）驱动电机转动。

整体设计示意图：四．系统组成以及系统各部分的设计：1.状态机的设计：状态机要完成的功能：1）能设置工作模式；2）控制洗涤、漂洗、干衣的驱动输出；3）能启动、暂停、停止洗衣机控制器；4）能重启、暂停和停止定时器；5）能接收定时器的到时标志；6）能使能键盘扫描计数器；7）能控制二路选择器。

状态机的输入：1）时钟(clk)；2）工作模式(modein(1DOWNTO0));3）启动（start)、停止(stop)、暂停(pause)；4）定时器标志(tcin)。

状态机的输出：1）洗涤、漂洗、干衣的驱动输出(wout(3downto0))；2）使能(ten)和停止(tstop)定时器;3）使能键盘扫描计数器(ken)；4）控制二路选择器(sel);5）运行模式(modeout(1DOWNTO0))。

状态图分析设计如下：状态机设计图：模块设计图：状态机仿真图如下：2.定时器设计：定时器的功能：1）能通过使能端暂停和允许定时器工作；2）能停止并复位定时器；3）能进行定时；4）能输出定时标志。

定时器的输入：1）时钟端(clk);2）使能端(ten)；3）停止复位端(tstop);4）预置分钟个位、分钟十位、秒个位、秒十位（smg,sms,ssg,sss)定时器的输出：计时分钟十位，分钟个位，秒十位，秒个位(oms,omg,oss,osg)模块设计图如下：定时器波形图如下：3.时间设置：时间设置键盘扫描器的功能：1）能响应按键；2）能在使能端的控制下工作。

时间设置键盘扫描器的输入：1）按键输入(kin);2）使能端(ken).时间设置键盘扫描器的输出：预置分钟个位、分钟十位、秒个位、秒十位（smg,sms,ssg,sss)模式设计图如下：波形图如下：4.模式设置:模式设置键盘扫描器的功能：预设工作模式，”000”为待机，”001”为洗涤，”010”为漂洗，”022”为干衣，”100”为暂停。

模式设计图如下：波形图如下：5.二路选择器：二路选择器的功能：设置显示运行时间还是设置时间，显示运行模式还是设置模式。

模式设计图如下：波形图如下：6.电机驱动器：模式设计图如下：波形图如下：五、整体结构图：整体波形图：六、实验心得：经过了这两个周的努力设计与思考，并在这次的实训设计的过程中我们有一些是实在在的心得：1、设计初期要明确题目的要求，根据要求去思考，构思大题的思路，并且了解课设过程可能要用到的芯片的功能及用法，可以在练习纸上将所要的逻辑进行抽象，演练，要思考全面，尽量避免在用软件设计过程中一次一次的改动。

2、方案确定后再开始设计。

设计时要注意对芯片的反馈控制及课程设计要求的紧急手动停止功能。

3、在设计某些模块的时候无法把握住整体，这时可以先进行小部分功能的实现，在此基础上进行改进，虽然可能会多花一些时间，但这比空想要有效的多。

4、尽可能是电路连线有序，模块之间关系清楚，既利于自己修改，也利于与别人交流。

5、注意多与同学交流意见，交流使自己获得更多信息，开拓了思路。

通过这次课程设计使我们发现了很多自己在EDA学习中被忽略的问题，一些重点。

从一次次的程序的调试中发现了自己在程序设计中的弱项，为自己敲了一个警钟。

更是我们充分的认识到不断学习、不断探索的重要性。

通过查阅其它资料丰富了我们的知识，是我们所能学到的东西不仅仅是局限于课堂上，加强了我们自主学习的积极性。

并且从同学的相互交流中弥补了自身的弱点。

形成了一种你争我赶的良好学风。

因为这次课设题目的新颖，更提高了我们的自主创新能力，大幅的提高了我们的学习效率，快速的实现了学以致用的目的。

因此，通过这次课程我们受益匪浅。

总之，要完成实验应该有较好的理论基础，整个实验都是在理论的指导下完成的，并且设计过程中使用了许多理论课上学的内容，如数据选择器，减法计数器等。

本次设计把理论应用到了实践中，通过设计，不但加深了我们对理论知识的理解和掌握，还加深了我们动手操作的能力。

当我们在实验设计过程遇到的挫折带给我们的不仅仅是悲痛的挫败感，更重要的是会给自己带来了一份成功时的喜悦，无形之中增加了我们的自信心，让我们在以后的大学生活中更加自信坚定的去面对每一困难与挫折。

七、附录：1.状态机的编程：LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY synopsys;USE synopsys.attributes.all;ENTITY SHELL_XIYIJI ISPORT(CLK,modein0,modein1,modein2,pause,start,stop,tcin:IN std_logic;ken,modeout0,modeout1,modeout2,sel,ten,tstop,wout0,wout1,wout2:OUTstd_logic);ATTRIBUTE async_set_reset OF stop:signal is"true";END;ARCHITECTURE BEHAVIOR OF SHELL_XIYIJI IS--State variables for machine sregSIGNAL dry,next_dry,ready,next_ready,rinse,next_rinse,waitup,next_waitup,wash,next_wash:std_logic;SIGNAL next_ken,next_modeout0,next_modeout1,next_modeout2,next_sel,next_ten, next_tstop,next_wout0,next_wout1,next_wout2:std_logic;SIGNAL modeout:std_logic_vector(2DOWNTO0);SIGNAL wout:std_logic_vector(2DOWNTO0);BEGINPROCESS(CLK,stop,next_dry,next_ready,next_rinse,next_waitup,next_wash ,next_ken,next_sel,next_ten,next_tstop,next_modeout2,next_modeout1,next_modeout0,next_wout2,next_wout1,next_wout0)BEGINIF(stop='1')THENdry<='0';ready<='1';rinse<='0';waitup<='0';wash<='0';sel<='0';ken<='1';ten<='1';tstop<='1';modeout2<='0';modeout1<='0';modeout0<='0';wout2<='0';wout1<='0';wout0<='0';ELSIF CLK='1'AND CLK'event THENdry<=next_dry;ready<=next_ready;rinse<=next_rinse;waitup<=next_waitup;wash<=next_wash;ken<=next_ken;sel<=next_sel;ten<=next_ten;tstop<=next_tstop;modeout2<=next_modeout2;modeout1<=next_modeout1;modeout0<=next_modeout0;wout2<=next_wout2;wout1<=next_wout1;wout0<=next_wout0;END IF;END PROCESS;PROCESS(dry,modein0,modein1,modein2,pause,ready,rinse,start,tcin,waitup, wash,modeout,wout)BEGINIF((tcin='0'AND pause='0'AND(dry='1'))OR(modein0='1'ANDmodein1='1'AND modein2='0'AND start='1'AND(ready='1'))OR(tcin='0'ANDmodein0='1'AND modein1='1'AND modein2='0'AND pause='0'AND(waitup='1')))THEN next_dry<='1';ELSE next_dry<='0';END IF;IF((tcin='1'AND(dry='1'))OR(start='0'AND(ready='1'))OR(modein2='1'AND(ready='1'))OR(modein0='0'AND modein1='0'AND(ready='1'))OR(tcin='1'AND(rinse='1'))OR(tcin='1'AND(wash='1')))THEN next_ready<='1';ELSE next_ready<='0';END IF;IF((modein0='0'AND modein1='1'AND modein2='0'AND start='1'AND( ready='1'))OR(tcin='0'AND pause='0'AND(rinse='1'))OR(tcin='0'ANDmodein0='0'AND modein1='1'AND modein2='0'AND pause='0'AND(waitup='1')))THEN next_rinse<='1';ELSE next_rinse<='0';END IF;IF((tcin='0'AND pause='1'AND(dry='1'))OR(tcin='0'AND pause='1'AND(rinse='1'))OR(pause='1'AND(waitup='1'))OR(modein2='1'AND(waitup='1'))OR(modein0='0'AND modein1='0'AND(waitup='1'))OR(tcin='1'AND(waitup='1'))OR(tcin='0'AND pause='1'AND(wash='1')))THEN next_waitup<='1';ELSE next_waitup<='0';END IF;IF((modein0='1'AND modein1='0'AND modein2='0'AND start='1'AND( ready='1'))OR(tcin='0'AND modein0='1'AND modein1='0'AND modein2='0'ANDpause='0'AND(waitup='1'))OR(tcin='0'AND pause='0'AND(wash='1')))THEN next_wash<='1';ELSE next_wash<='0';END IF;IF((tcin='1'AND(dry='1'))OR(start='0'AND(ready='1'))OR(modein2='1'AND(ready='1'))OR(modein0='0'AND modein1='0'AND(ready='1'))OR(tcin='1'AND(rinse='1'))OR(tcin='1'AND(wash='1')))THEN next_ken<='1';ELSE next_ken<='0';END IF;modeout<=((std_logic_vector'(dry,dry,dry))AND((std_logic_vector' (NOT tcin,NOT tcin,NOT tcin)AND std_logic_vector'(NOT pause,NOT pause, NOT pause)))AND(std_logic_vector'("011")))OR((std_logic_vector'(ready,ready,ready))AND((std_logic_vector'(modein0,modein0,modein0)AND std_logic_vector'(modein1,modein1,modein1)AND std_logic_vector'(NOT modein2,NOT modein2,NOT modein2)AND std_logic_vector'(start,start,start)))AND(std_logic_vector'("011")))OR((std_logic_vector'(waitup,waitup,waitup))AND((std_logic_vector'(NOT tcin,NOT tcin,NOTtcin)AND std_logic_vector'(modein0,modein0,modein0)AND std_logic_vector' (modein1,modein1,modein1)AND std_logic_vector'(NOT modein2,NOT modein2, NOT modein2)AND std_logic_vector'(NOT pause,NOT pause,NOT pause)))AND (std_logic_vector'("011")))OR((std_logic_vector'(dry,dry,dry))AND((std_logic_vector'(tcin,tcin,tcin)))AND(std_logic_vector'("000")))OR((std_logic_vector'(ready,ready,ready))AND((std_logic_vector'(NOT modein0,NOT modein0,NOT modein0)ANDstd_logic_vector'(NOT modein1,NOT modein1,NOT modein1))OR(std_logic_vector'(modein2,modein2,modein2))OR(std_logic_vector'(NOTstart,NOT start,NOT start)))AND(std_logic_vector'("000")))OR((std_logic_vector'(rinse,rinse,rinse))AND((std_logic_vector'(tcin,tcin,tcin)))AND(std_logic_vector'("000")))OR((std_logic_vector'(wash,wash,wash))AND((std_logic_vector'(tcin,tcin,tcin)))AND(std_logic_vector'("000")))OR((std_logic_vector'(ready,ready,ready))AND((std_logic_vector'(NOT modein0,NOT modein0,NOT modein0)ANDstd_logic_vector'(modein1,modein1,modein1)AND std_logic_vector'(NOTmodein2,NOT modein2,NOT modein2)AND std_logic_vector'(start,start,start)))AND(std_logic_vector'("010")))OR((std_logic_vector'(rinse,rinse,rinse))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)ANDstd_logic_vector'(NOT pause,NOT pause,NOT pause)))AND(std_logic_vector'("010")))OR((std_logic_vector'(waitup,waitup,waitup))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)ANDstd_logic_vector'(NOT modein0,NOT modein0,NOT modein0)ANDstd_logic_vector'(modein1,modein1,modein1)AND std_logic_vector'(NOTmodein2,NOT modein2,NOT modein2)AND std_logic_vector'(NOT pause,NOTpause,NOT pause)))AND(std_logic_vector'("010")))OR((std_logic_vector'(dry,dry,dry))AND((std_logic_vector'(NOT tcin,NOTtcin,NOT tcin)AND std_logic_vector'(pause,pause,pause)))AND(std_logic_vector'("100")))OR((std_logic_vector'(rinse,rinse,rinse))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)ANDstd_logic_vector'(pause,pause,pause)))AND(std_logic_vector'("100")))OR((std_logic_vector'(waitup,waitup,waitup))AND((std_logic_vector'(tcin,tcin,tcin))OR(std_logic_vector'(NOT modein0,NOT modein0,NOT modein0)AND std_logic_vector'(NOT modein1,NOT modein1,NOT modein1))OR(std_logic_vector'(modein2,modein2,modein2))OR(std_logic_vector'(pause,pause,pause)))AND(std_logic_vector'("100")))OR((std_logic_vector'(wash,wash,wash))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)AND std_logic_vector'(pause,pause,pause)))AND(std_logic_vector'("100")))OR((std_logic_vector'(ready,ready,ready))AND((std_logic_vector'(modein0,modein0,modein0)ANDstd_logic_vector'(NOT modein1,NOT modein1,NOT modein1)ANDstd_logic_vector'(NOT modein2,NOT modein2,NOT modein2)ANDstd_logic_vector'(start,start,start)))AND(std_logic_vector'("001")))OR((std_logic_vector'(waitup,waitup,waitup))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)AND std_logic_vector'(modein0,modein0,modein0)AND std_logic_vector'(NOT modein1,NOT modein1,NOT modein1)AND std_logic_vector'(NOT modein2,NOT modein2,NOT modein2)AND std_logic_vector'(NOT pause,NOT pause,NOT pause)))AND(std_logic_vector'("001")))OR((std_logic_vector'(wash,wash,wash))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)ANDstd_logic_vector'(NOT pause,NOT pause,NOT pause)))AND(std_logic_vector'("001")));IF((modein1='1'AND modein2='0'AND start='1'AND(ready='1'))OR(tcin='0'AND(dry='1'))OR(tcin='0'AND(rinse='1'))OR(modein0='1'ANDmodein2='0'AND start='1'AND(ready='1'))OR((waitup='1'))OR(tcin='0'AND(wash='1')))THEN next_sel<='1';ELSE next_sel<='0';END IF;IF((tcin='1'AND(dry='1'))OR(start='0'AND(ready='1'))OR(modein2='1'AND(ready='1'))OR(modein0='0'AND modein1='0'AND(ready='1'))OR(tcin='1'AND(rinse='1'))OR(tcin='1'AND(wash='1')))THEN next_ten<='1';ELSE next_ten<='0';END IF;IF((pause='0'AND(dry='1'))OR(tcin='1'AND(dry='1'))OR(tcin='1' AND(rinse='1'))OR(tcin='1'AND(wash='1'))OR(pause='0'AND(rinse='1'))OR(tcin='0'AND modein1='1'AND modein2='0'AND pause='0'AND(waitup='1'))OR((ready='1'))OR(tcin='0'AND modein0='1'ANDmodein2='0'AND pause='0'AND(waitup='1'))OR(pause='0'AND(wash='1')))THEN next_tstop<='1';ELSE next_tstop<='0';END IF;wout<=((std_logic_vector'(dry,dry,dry))AND((std_logic_vector'( NOT tcin,NOT tcin,NOT tcin)AND std_logic_vector'(NOT pause,NOT pause,NOT pause)))AND(std_logic_vector'("011")))OR((std_logic_vector'(ready,ready,ready))AND((std_logic_vector'(modein0,modein0,modein0)AND std_logic_vector'(modein1,modein1,modein1)AND std_logic_vector'(NOT modein2,NOT modein2,NOT modein2)AND std_logic_vector'(start,start,start)))AND(std_logic_vector'("011")))OR((std_logic_vector'(waitup,waitup,waitup))AND((std_logic_vector'(NOT tcin,NOT tcin,NOTtcin)AND std_logic_vector'(modein0,modein0,modein0)AND std_logic_vector' (modein1,modein1,modein1)AND std_logic_vector'(NOT modein2,NOT modein2, NOT modein2)AND std_logic_vector'(NOT pause,NOT pause,NOT pause)))AND (std_logic_vector'("011")))OR((std_logic_vector'(dry,dry,dry))AND((std_logic_vector'(tcin,tcin,tcin)))AND(std_logic_vector'("000")))OR((std_logic_vector'(ready,ready,ready))AND((std_logic_vector'(NOT modein0,NOT modein0,NOT modein0)ANDstd_logic_vector'(NOT modein1,NOT modein1,NOT modein1))OR(std_logic_vector'(modein2,modein2,modein2))OR(std_logic_vector'(NOTstart,NOT start,NOT start)))AND(std_logic_vector'("000")))OR((std_logic_vector'(rinse,rinse,rinse))AND((std_logic_vector'(tcin,tcin,tcin)))AND(std_logic_vector'("000")))OR((std_logic_vector'(wash,wash,wash))AND((std_logic_vector'(tcin,tcin,tcin)))AND(std_logic_vector'("000")))OR((std_logic_vector'(ready,ready,ready))AND((std_logic_vector'(NOT modein0,NOT modein0,NOT modein0)ANDstd_logic_vector'(modein1,modein1,modein1)AND std_logic_vector'(NOTmodein2,NOT modein2,NOT modein2)AND std_logic_vector'(start,start,start)))AND(std_logic_vector'("010")))OR((std_logic_vector'(rinse,rinse,rinse))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)ANDstd_logic_vector'(NOT pause,NOT pause,NOT pause)))AND(std_logic_vector'("010")))OR((std_logic_vector'(waitup,waitup,waitup))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)ANDstd_logic_vector'(NOT modein0,NOT modein0,NOT modein0)ANDstd_logic_vector'(modein1,modein1,modein1)AND std_logic_vector'(NOTmodein2,NOT modein2,NOT modein2)AND std_logic_vector'(NOT pause,NOTpause,NOT pause)))AND(std_logic_vector'("010")))OR((std_logic_vector'(dry,dry,dry))AND((std_logic_vector'(NOT tcin,NOTtcin,NOT tcin)AND std_logic_vector'(pause,pause,pause)))AND(std_logic_vector'("100")))OR((std_logic_vector'(rinse,rinse,rinse))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)ANDstd_logic_vector'(pause,pause,pause)))AND(std_logic_vector'("100")))OR((std_logic_vector'(waitup,waitup,waitup))AND((std_logic_vector'(tcin,tcin,tcin))OR(std_logic_vector'(NOT modein0,NOT modein0,NOT modein0)AND std_logic_vector'(NOT modein1,NOT modein1,NOT modein1))OR(std_logic_vector'(modein2,modein2,modein2))OR(std_logic_vector'(pause,pause,pause)))AND(std_logic_vector'("100")))OR((std_logic_vector'(wash,wash,wash))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)AND std_logic_vector'(pause,pause,pause)))AND(std_logic_vector'("100")))OR((std_logic_vector'(ready,ready,ready))AND((std_logic_vector'(modein0,modein0,modein0)ANDstd_logic_vector'(NOT modein1,NOT modein1,NOT modein1)ANDstd_logic_vector'(NOT modein2,NOT modein2,NOT modein2)ANDstd_logic_vector'(start,start,start)))AND(std_logic_vector'("001")))OR((std_logic_vector'(waitup,waitup,waitup))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)AND std_logic_vector'(modein0,modein0,modein0)AND std_logic_vector'(NOT modein1,NOT modein1,NOT modein1)AND std_logic_vector'(NOT modein2,NOT modein2,NOT modein2)ANDstd_logic_vector'(NOT pause,NOT pause,NOT pause)))AND(std_logic_vector'("001")))OR((std_logic_vector'(wash,wash,wash))AND((std_logic_vector'(NOT tcin,NOT tcin,NOT tcin)ANDstd_logic_vector'(NOT pause,NOT pause,NOT pause)))AND(std_logic_vector'("001")));next_modeout2<=modeout(2);next_modeout1<=modeout(1);next_modeout0<=modeout(0);next_wout2<=wout(2);next_wout1<=wout(1);next_wout0<=wout(0);END PROCESS;END BEHAVIOR;LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY synopsys;USE synopsys.attributes.all;ENTITY XIYIJI ISPORT(modein:IN std_logic_vector(2DOWNTO0);modeout:OUT std_logic_vector(2DOWNTO0);wout:OUT std_logic_vector(2DOWNTO0);CLK,pause,start,stop,tcin:IN std_logic;ken,sel,ten,tstop:OUT std_logic);END;ARCHITECTURE BEHAVIOR OF XIYIJI ISCOMPONENT SHELL_XIYIJIPORT(CLK,modein0,modein1,modein2,pause,start,stop,tcin:IN std_logic;ken,modeout0,modeout1,modeout2,sel,ten,tstop,wout0,wout1,wout2:OUTstd_logic);END COMPONENT;BEGINSHELL1_XIYIJI:SHELL_XIYIJI PORT MAP(CLK=>CLK,modein0=>modein(0),modein1=> modein(1),modein2=>modein(2),pause=>pause,start=>start,stop=>stop,tcin=>tcin,ken=>ken,modeout0=>modeout(0),modeout1=>modeout(1),modeout2=>modeout(2),sel=>sel,ten=>ten,tstop=>tstop,wout0=>wout(0),wout1=>wout(1),wout2=>wout(2));END BEHAVIOR;2.定时器的编程：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xiyiji6ISPORT(clk:IN STD_LOGIC;ten,tstop:IN STD_LOGIC;sms:IN INTEGER RANGE0TO3;sss:IN INTEGER RANGE0TO6;smg,ssg:IN INTEGER RANGE0TO9;cin:OUT STD_LOGIC;oms:BUFFER INTEGER RANGE0TO3;oss:BUFFER INTEGER RANGE0TO6;omg,osg:BUFFER INTEGER RANGE0TO9);END xiyiji6;ARCHITECTURE one OF xiyiji6ISBEGINPROCESS(clk,ten,tstop)BEGINIF ten='1'THENIF tstop='1'THEN osg<=ssg;ELSIF clk'EVENT AND clk='1'THENIF osg=0THENIF oss>0OR omg>0OR oms>0THEN osg<=9; ELSE osg<=0;END IF;ELSE osg<=osg-1;END IF;END IF;END IF;END PROCESS;PROCESS(clk,ten,tstop,osg)BEGINIF ten='1'THENIF tstop='1'THEN oss<=sss;ELSIF clk'EVENT AND clk='1'THENIF osg=0THENIF oss=0THENIF omg>0OR oms>0THEN oss<=5;ELSE oss<=0;END IF;ELSE oss<=oss-1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(clk,ten,tstop,osg,oss)BEGINIF ten='1'THENIF tstop='1'THEN omg<=smg;ELSIF clk'EVENT AND clk='1'THENIF oss=0THENIF omg=0THENIF oms>0THEN omg<=9;ELSE omg<=0;END IF;ELSE omg<=omg-1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(clk,ten,tstop,osg,oss,omg)BEGINIF ten='1'THENIF tstop='1'THEN oms<=sms;ELSIF clk'EVENT AND clk='1'THENIF omg=0THENIF oms=0THEN oms<=0;ELSE oms<=oms-1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(clk,ten,tstop,osg,oss,omg,oms)BEGINIF ten='1'THENIF tstop='0'THENIF clk'EVENT AND clk='1'THENIF oms=0AND omg=0AND oss=0AND osg=1THEN cin<='1'; ELSE cin<='0';END IF;END IF;END IF;END IF;END PROCESS;END one;3.时间设置的编程：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY XIYIJI ISPORT(kin:IN STD_LOGIC;ken:IN STD_LOGIC;sms:BUFFER INTEGER RANGE0TO3;sss:BUFFER INTEGER RANGE0TO6;smg,ssg:BUFFER INTEGER RANGE0TO9);END XIYIJI; ARCHITECTURE one OF XIYIJI IS BEGINPROCESS(kin,ken)BEGINIF ken='1'THENIF kin'EVENT AND kin='1'THEN IF ssg=9THENssg<=0;ELSEssg<=ssg+1;END IF;END IF;END IF;END PROCESS;PROCESS(kin,ken,ssg)BEGINIF ken='1'THENIF kin'EVENT AND kin='1'THEN IF ssg=9THENIF sss=5THENsss<=0;ELSEsss<=sss+1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(kin,ken,ssg,sss) BEGINIF ken='1'THENIF kin'EVENT AND kin='1'THEN IF sss=5AND ssg=9THENIF smg=9THENsmg<=0;ELSEsmg<=smg+1;END IF;END IF;END IF;END PROCESS;PROCESS(kin,ken,ssg,sss,smg)BEGINIF ken='1'THENIF kin'EVENT AND kin='1'THENIF smg=9AND sss=5AND ssg=9THENIF sms=2THENsms<=0;ELSEsms<=sms+1;END IF;END IF;END IF;END IF;END PROCESS;END one;4.模式设置：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY xiyiji4ISPORT(kin:IN STD_LOGIC;ken:IN STD_LOGIC;modeset:BUFFER STD_LOGIC_VECTOR(2DOWNTO0)); END xiyiji4;ARCHITECTURE one OF xiyiji4ISBEGINPROCESS(kin,ken)BEGINIF ken='1'THENIF kin'EVENT AND kin='1'THENIF modeset>="011"THEN modeset<="001";ELSE modeset<=modeset+1;END IF;END IF;END PROCESS;END one;5.二路选择器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xiyiji5ISPORT(oms:IN INTEGER RANGE0TO3;oss:IN INTEGER RANGE0TO6;omg,osg:IN INTEGER RANGE0TO9;sms:IN INTEGER RANGE0TO3;sss:IN INTEGER RANGE0TO6;smg,ssg:IN INTEGER RANGE0TO9;modeset:IN STD_LOGIC_VECTOR(2DOWNTO0);modeout:IN STD_LOGIC_VECTOR(2DOWNTO0);sel:IN STD_LOGIC;msdis:OUT INTEGER RANGE0TO3;mgdis:OUT INTEGER RANGE0TO9;ssdis:OUT INTEGER RANGE0TO6;sgdis:OUT INTEGER RANGE0TO9;modedis:OUT STD_LOGIC_VECTOR(2DOWNTO0));END xiyiji5;ARCHITECTURE one OF xiyiji5ISBEGINPROCESS(sel,oms,oss,omg,osg,sms,sss,smg,ssg,modeset,modeout) BEGINIF sel='1'THENmsdis<=oms;mgdis<=omg;ssdis<=oss;sgdis<=osg;modedis<=modeout;ELSEmsdis<=sms;mgdis<=smg;ssdis<=sss;sgdis<=ssg;modedis<=modeset;END IF;END PROCESS;6.电机驱动器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY xiyiji3ISPORT(win:IN STD_LOGIC_VECTOR(2DOWNTO0);clk:IN STD_LOGIC;fw,bw:OUT STD_LOGIC);END xiyiji3;ARCHITECTURE one OF xiyiji3ISBEGINPROCESS(clk,win)VARIABLE d,cnt8:STD_LOGIC_VECTOR(7DOWNTO0); VARIABLE fout:STD_LOGIC;BEGINCASE win ISWHEN"000"=>fw<='0';bw<='0'; WHEN"001"=>d:="00111111";fw<=fout;bw<='0'; WHEN"010"=>d:="00001111";fw<='0';bw<=fout; WHEN"100"=>d:="01111111";fw<=fout;bw<='0'; WHEN OTHERS=>fw<='0';bw<='0';END CASE;IF clk'EVENT AND clk='1'THENIF CNT8="11111111"THENCNT8:="00000000";fout:='1';ELSECNT8:=CNT8+1;IF CNT8>d THENfout:='0';END IF;END IF;END IF;END PROCESS;END one;。