静态显示
library ieee;
use ieee.std_logic_1164.all;
entity bcd_seg is
port(
a,b,c,d:in std_logic;
seg:out std_logic_vector(7 downto 0)
);
end entity bcd_seg;
architecture one of bcd_seg is
signal bcd:std_logic_vector(3 downto 0);
begin
bcd<=a&b&c&d;
process(bcd)
begin
case bcd is
when "0000"=>seg<="00111111";
when "0001"=>seg<="00000110";
when "0010"=>seg<="01011011";
when "0011"=>seg<="01001111";
when "0100"=>seg<="01100110";
when "0101"=>seg<="01101101";
when "0110"=>seg<="01111101";
when "0111"=>seg<="00000111";
when "1000"=>seg<="01111111";
when "1001"=>seg<="01101111";
when others=>null;
end case;
end process;
end architecture one;
动态显示
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcd_seg is
port(
clk:in std_logic;
a,b,c,d:in std_logic;
com:out std_logic_vector(2 downto 0);
seg:out std_logic_vector(7 downto 0)
);
end entity bcd_seg;
architecture one of bcd_seg is
signal cnt:std_logic_vector(2 downto 0);
signal bcd:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if cnt="111" then
cnt<="000";
else
cnt<=cnt+'1';
end if;
end if;
end process;
com<=cnt;
bcd<=a&b&c&d;
process(bcd)
begin
case bcd is
when "0000"=>seg<="00111111";
when "0001"=>seg<="00000110";
when "0010"=>seg<="01011011";
when "0011"=>seg<="01001111";
when "0100"=>seg<="01100110";
when "0101"=>seg<="01101101";
when "0110"=>seg<="01111101";
when "0111"=>seg<="00000111";
when "1000"=>seg<="01111111";
when "1001"=>seg<="01101111";
when "1010"=>seg<="01110111";
when "1011"=>seg<="01111100";
when "1100"=>seg<="00111001";
when "1101"=>seg<="01011110";
when "1110"=>seg<="01111001";
when "1111"=>seg<="01110001";
end case;
end process;
end architecture one;。