DDS devices to produce high-quality waveform: a simple, efficient and flexibleAbstract: Direct digital frequency synthesis (DDS) technology for the generation and regulation of high-quality waveforms, widely used in medical, industrial, instrumentation, communications, defense and many other areas. This article will briefly describe the technology, on its strengths and weaknesses, examine some application examples, and also introduced some new products that contribute to the promotion1.IntroductionA key requirement in many industries is an exact production, easy operation and quick change of different frequencies, different types of waveforms. Whether it is broadband transceiver requires low phase noise and excellent spurious-free dynamic performance of agile frequency source, or for industrial measurement and control system needs a stable frequency excitation, fast, easy and economical to produce adjustable waveform while maintaining phase continuity capabilities are critical to a design standard, which is what the advantages of direct digital frequency synthesis.2.Frequency synthesis taskThe growing congestion of the spectrum, coupled with lower power consumption, quality of never-ending demand for higher measuring equipment, these factors require the use of the new frequency range, requires a better use of existing frequency range. A result, the search for better control, in most cases, by means of frequency synthesizer for frequency generation. These devices use a given frequency, fC of to generate a target frequency (and phase) fOUT the general relationship can be simply expressed as:fOUT = εx× fCAmong them, the scale factor εx, sometimes known as the normalized frequency.The equation is usually gradual approximation of the real number algorithms. When the scale factor is a rational number, two relatively prime numbers (output frequency and reference frequency) than the harmonic. However, in most cases, εx may belong to a broader set of real numbers, the approximation process is within the acceptable range will be truncatedThe frequency synthesizer a practical way to achieve is the direct digital frequency synthesis (of DDFS), usually referred to as direct digital synthesis (DDS). This technique using digital data processing to generate a frequency and phase adjustable output, the output anda fixed frequency reference clock source fC. related. DDS architecture, the reference or the system clock frequency divided by a scale factor to produce the desired frequency, the scale factor is controlled by the binary tuning word programmable.In short, direct digital frequency synthesizer to convert a bunch of clock pulses into an analog waveform, usually a sine wave, triangle wave or square wave. Shown in Figure 1, its main parts: the phase accumulator (to produce the output waveform phase angle data), relative to digital converter, (above the phase data isconverted to the instantaneous output amplitude data), and digital-to-analog converter (DAC) (the magnitude of data into a sampled analog data points)Figure 2-1 DDS function of the system block diagram.For the sine wave output, relative to digital converter is usually a sine lookup table (Figure 2). Phase accumulator unit count N a relative to the frequency of fC, according to the following equation:The number of pulses of the fC:M is the resolution of the tuning word (24-48)N corresponds to the smallest increment of phase change of the phase accumulator output wordFigure2-2 Typical DDS architecture and signal path (with DACs).Changing N will immediately change the output phase and frequency, so the system has its own continuous phase characteristics, which is one of the key attributes of many applications. No loop settling time, which is different from the analog system, such as phase-locked loops (PLLs). DAC is usually a high-performance circuit, designed specifically for the DDS core (phase accumulator and phase amplitude converter). In most cases, the results of the device (usually single-chip) is generally referred to as the pure DDS or the C-DDS.Actual DDS devices are generally multiple registers, in order to achieve a different frequency and phasemodulation scheme. Such as phase register, their storage phase of increase in the output phase of the phase accumulator. In this way, the corresponding delay output sine wave phase in a phase tuning word. This is useful for phase modulation applications for communication systems. The resolution of the adder circuit determines the number of bits of the phase tuning word, therefore, also decided to delay the resolution.Integrated in a single device on the engine of a DDS and a DAC has both advantages and disadvantages, however, whether integrated or not, need a DAC to produce ultra-high purity high-quality analog signal. DAC will convert digital sinusoidal output to an analog sine wave may be single-ended or differential. Some of the key requirements for low phase noise, excellent wideband (WB) and narrowband (NB), spurious-free dynamic range (SFDR), and low power consumption. If the external device, the DAC must be fast enough to handle the signal, so the built-in parallel port device is very common.3.DDS and other solutionsThe frequency analog phase-locked loops (PLLs), clock generator, and the use of FPGA dynamic programming of the output of the DAC. By examining the spectrum of performance and power of these technologies, a simple comparison, Table 1 shows the qualitative results of the comparisonTable 3-1DDS with competing technologies - Advanced comparePower consumption Spectral purity RemarksDDS Low Middle Ease of tuningDiscrete DAC+FPGA Middle Middle-High With tuning capabilitiesAnalog PLL Milddle High Difficult tuningPhase-locked loop is a feedback loop and its components: a phase comparator, a divider and a pressure-controlled oscillator (VCO), phase comparator reference frequency and output frequency (usually the output frequency is N)frequency) were compared. The error voltage generated by the phase comparator is used to adjust the VCO, thus the output frequency. When the loop is established, the output frequency and / or phase with the reference frequency to maintain a precise relationship. PLL has long been considered in a particular frequency range, high fidelity and consistent signal low phase noise and high spurious free dynamic range (SFDR) are ideal for applications.PLL can not be precisely and quickly tuning the frequency output waveform, and the slow response, which limits their applicability for fast frequency hopping and part of the frequency shift keying and phase shift keying applications.Other programs, including integrated DDS engine field programmable gate arrays (FPGAs) - a synthetic sine wave output with the off-the-shelf DAC - though the PLL frequency-hopping problem can be solved, but there own shortcomings. The defects of the major systems work and interface power requirements, high cost, large size, and system developers must also consider the additional software, hardware and memory. For example, using the DDS engine option in the modern FPGA to generate the 10 MHz output signal dynamic range is 60 dB up to 72 kB memory space. In addition, designers need to accept and be familiar with thesubtle balance DDS core architecture. .From a practical point of view (see Table 2), thanks to the rapid development of CMOS technology and modern digital design techniques, as well as the improvement of the DAC topology, DDS technology has been able to achieve unprecedented low power consumption in a wide range of applications, spectrum performance and cost levels. Although the pure DDS products in performance and design flexibility to achieve the level of high-end DAC technology and FPGA, but the advantages of DDS in terms of size, power consumption, cost and simplicity, making it the primary choice for many applications.Table 3-2 Benchmark Analysis Summary - frequency generation technique (<50 MHz)Phase -locked loop DAC + FPGA DDS Spectral performance High High MiddleSystem power requirements High High MiddleDigital frequency tuning No Yes YesTuning response time High Low LowSolution size Middle High LowWaveform flexibility Low Middle HighCost Middle High LowDesign reuse Middle Low HighImplementation complexity Middle High LowAlso be noted that the DDS device for digital methods to produce the output waveform, it can simplify some of the architecture of the solution, or the waveform of digital programming to create the conditions. Usually with a sine wave to explain the functions and working principle of the DDS, but using modern DDS ICs can easily generate a triangle wave or square wave (clock) output, thereby eliminating the former case the lookup table, and the latter case the DAC the need to integrate a simple and accurate enough.4. Performance and limitations of the DDS4.1 Image and envelope: Sin (x) xx roll-offThe actual output of the DAC is not a continuous sine wave, but a series of pulses with a sinusoidal time envelope. The corresponding spectrum is a series of image and signal aliasing. Image along the sin (x) / x envelope distribution (see Figure 3 | margin | graph). The need for the filter to suppress frequencies outside the target band, but can not inhibit the high-level in the passband aliasing (for example, caused due to DAC non-linear)The Nyquist criterion requires that each cycle requires at least two sampling points in order to rebuild the desired output waveform. The Mirroring response arising from sampling the output frequency K, CLOCK ×OUT In this example, which CLOCK = 25 25 MHz and fOUT = 5 MHz, the first and second mirror frequency appear in (see Figure 3) fCLOCK × fOUT, o 20 MHz and 30 MHz. The third and fourth mirror frequency at 45 MHz and 55 MHz. Note, sin (x) / x value of zero at multiples of the sampling frequency.When fOUT greater than the Nyquist bandwidth (1/2 f CLOCK), the first mirror frequency will appear in the Nyquist bandwidth, the occurrence of aliasing (such as 15 MHz signal aliasing down to 10 MHz). Can not use the traditional quist anti-aliasing filter to filter out aliasing mirror frequency from the outputFigure 4-1 Sin, in Figure 3.DDS, (x) / x roll-off.In a typical DDS application, the use of a low-pass filter to suppress the mirror frequency response of the output spectrum. To make the low-pass filter cutoff frequency to remain at reasonable levels, and keep it simple filter design, a feasible approach is the use of an economic low-pass output filter bandwidth limited to about 40% of the frequency of clock.Any given mirror frequency relative to the amplitude of the fundamental formula of sin (x) / x calculation. Because the function of the frequency roll-off, the basic output of the amplitude and the output frequency is inversely proportional to decrease; in the DDS system, reduce the amount of DC-Nyquist bandwidth range of -3.92 dB.Significant reduction in frequency in the first mirror - the fundamental 3 dB range. In order to simplify the DDS application filtering, frequency plan must be formulated and analyzed to mirror the frequency and magnitude of the sin (x) / x response in the OUT and CLOCK target frequency spectrum requirements. Other unwanted frequencies in the output spectrum (such as integral and differential linearity error of the DAC, the surge of energy associated with the DAC and clock feed through noise) does not follow the sin (x) / x roll-off response. These unwanted frequencies will be harmonic and spurious energy in the output spectrum in many places - but its magnitude is generally far below the mirror frequency response. DDS devices to the general background noise, substrate noise, thermal noise effects, ground coupling and other signal source coupling factor cumulative portfolio decisions. DDS devices, the noise floor performance of stray and jitter by the circuit board layout, power quality, and - most importantly - Enter the profound impact of the quality of the reference clock.4.2ShakeThe edge of the perfect clock source will be the precise time interval, the interval will never change. Of course, this is not possible; even the best oscillator is also the ideal components constitute, with noise and other defects. Quality and low phase noise crystal oscillator jitter picosecond, and is built up from one millionthe number of clock edge. The factors leading to jitter external interference, thermal noise, the oscillator circuit instability and power, ground and output connections bring, all these factors will interfere with the timing characteristics of the oscillator. In addition, the oscillator by the external magnetic field or electric field and the nearby transmitter RF interference. Oscillator circuit, a simple amplifier, inverter or buffer to signal additional jitter.Therefore, the choice of a low-jitter, and the edge of steep stable reference clock oscillator is critical. Higher frequency reference clock allows a larger sample, and divide to some extent, reduce the jitter, because the signal to divide a long time to produce the same amount of jitter, which can reduce the jitter on the signal percentage.4.3 Noise - including the phase noiseThe sampling system noise depends on many factors, the most important factor is the reference clock jitter, this jitter performance of phase noise on fundamental signal. In the DDS system, the register output of the truncated phase may bring the system error code. The binary word does not lead to the truncation error. But for non-binary word, phase noise truncation error in the spectrum spurious. Spurious frequency / amplitude depends on the code word. Quantification and linearity error of the DAC will be brought to the system harmonic noise. Time-domain error (such as owed to the red / overshoot and code errors) will increase the output signal distortion.5. Application5.1 DDS applications can be divided into two categories:Require agile frequency source for data coding and modulation applications, communications and radar systemsRequire measurement of the universal frequency synthesizer features and programmable tuning, scanning, and motivational skills, industrial and optical applicationsBoth cases, the trend toward higher spectral purity (low phase noise and higher spurious free dynamic range), also low power and small size requirements to accommodate the remote ordemand for battery-powered devices.5.2 Modulation / data encoding, and synchronization of the DDSDDS products first appeared on the radar and military applications and the development of some of its characteristics (performance improvements, cost and size, etc.) DDS technology is becoming more prevalent in the modulation and data encoding applications. This section will discuss the two data encoding scheme in the DDS system.5.3 Binary frequency shift keyingThe launch of the data is a continuous carrier frequency in two discrete frequency (binary one, ie, pass number, a binary 0, namely, the transformation between the space). Figure 4 shows the relationship between the data and transmit signals.Figure 5-1 binary FSK modulation.Binary 1 and 0 for two different frequencies f0 and f1, respectively. This encoding scheme can be easily DDS device. On behalf of the output frequency of the DDS frequency tuning word change to f0 and f1, will launch the 1 and 0. To transform the output frequency shall dedicated pin FSELECT, containing the appropriate tuning word registers (see Figure 5)Figure 5-2 AD9834 or AD9838 DDS tuning word selector realization of the FSK encoding.5.4 Phase shift keying (PSK)In PSK, the carrier frequency remains the same, by changing the phase of the transmitted signal to transmit information. Can take advantage of a variety of programs to achieve PSK,. The easiest way is often referred to as binary PSK (BPSK), using only two signal phase: 0 ° (logic 1) and 180 ° (logic 0). Members state depends on the status of the former one. If the wave phase remains unchanged, the signal state will remain the same (low or high). Wave phase change 180 °, ie, phase inversion, the signal state will change (low into high or high to low). PSK coding in DDS products can be easily achieved, because most devices have a separate input register (phase register), and phase values can be loaded. This value is added directly to the carrier phase, without changing its frequency. Change the contents of the register will be modulated carrier phase, resulting in a PSK output. For applications that require high-speed modulation, built-in phase register of the AD9834 and AD9838 allow PSELECT pin signal transformation, according to need modulated carrierin the preloaded phase registers.The more complex the PSK four or eight-wave phase. Thus, whenever the phase change of binary data transfer rate will be higher than the BPSK modulation. In the four-phase modulation (Quadrature PSK), in the phase angle of 0 ° to +90 °, -90 ° and +180 °; each phase to transform the two signals may represent a factor AD9830, AD9831, AD9832, and the AD9835 provides four phase registers, can be continuously updated register of different phase shift, the complex phase modulation scheme.5.5 The use of synchronous mode of multiple DDS devices to achieve the I / QMultiple DDS components to achieve the many applications of the I / Q sine wave or square wave signal of known phase relationship between two or more synchronous mode. A common example is the same phase and quadrature modulation (I / Q) in this technique, the phase angle of 0 ° and 90 ° from the carrier frequency signal information. To run two separate DDS components, you can use the same source clock to output can directly control and manipulate the signal of the phase relationship. In Figure 6, with a reference clock on the AD9838 device programming; the RESET pin is used to update the two devices. In this way, you can achieve a simple I / Q modulationRESET after power and initialized before any data to the DDS transmission. DDS output results can be placed in a known phase, making it a common reference point of view, in order to synchronize multiple DDS devices. When new data is sent to multiple DDS devices, the DDS can remain relevant phase relationship, or by the phase offset register can predict the relative phase shift between the adjustments of multiple DDS. The AD983x series of DDS products have a 12 phase resolution, the effective resolution of 0.1 °.Figure 5-3 Synchronize the two DDS components.DDS器件产生高质量波形：简单、高效而灵活摘要:直接数字频率合成(DDS)技术用于产生和调节高质量波形，广泛用于医学、工业、仪器仪表、通信、国防等众多领域。