描述CMOS工艺14个步骤的主要目的
4.
Discuss the key process and equipment used in each CMOS manufacturing step.
能讨论每一步流程的关键工艺和设备
Major Fabrication Steps in MOS Process Flow
Extraction assembly Analyzing magnet
Ion beam
Lighter ions
Process chamber
Heavy ions
Scanning disk
Graphite
Thin Film Metallization Bay
Simplified Schematics of CVD Processing System
top nitride
G D S G D S G D
Ion Implantation
Active Regions
Nitride Deposition
Contact Etch
Metal Deposition and Etch
CMOS Process Flow
• Overview of Areas in a Wafer Fab
– – – – – – Diffusion Photolithography Etch Ion Implant Thin Films Polish
Model of Typical Wafer Flow in a Sub-Micron CMOS IC Fab
Wafer Fabrication (front-end)
Gate Structure 多晶硅栅结构 Lightly Doped Drain Implants 轻掺杂漏注入 Sidewall Spacer 侧墙形成 Source/Drain Implants 源/漏注入 Contact Formation 接触孔形成
8
n+ LI metal M-3
13
ILD-4
Quartz tube
Temperaturesetting voltages
Heater 1
Heater 2
Heater 3 Three-zone Heating Elements
Pressure controller
Exhaust
Photolithography Bay in a Sub-micron Wafer Fab
12
M-2
ILD-3
11
M-1
ILD-2
10
ILD-1
Via
9
Poly gate
3
p+
5
p+
LI oxide STI n+ n+ p+
2 7
4
n-well
6
p-well
1
pEpitaxial layer
p+ Silicon substrate
CMOS Manufacturing Steps
8. 9. Local Interconnect 局部互连 Interlayer Dielectric to Via-1 通孔1和金属塞1的形成 10. First Metal Layer 金属1互连 11. Second ILD to Via-2 通孔2和金属塞2的形成 12. Second Metal Layer to Via-3
9、清洗 10、 1000 C干氧，~150Ǻ；保护外延层 11、Si3N4膜淀积：~750C LPCVD NH3+SiH2Cl2 ；保护有源区； CMP的阻挡材料 12、第三层掩膜：检测；由于特征尺寸减小，光刻难度增加。 13、STI槽刻蚀：F基或Cl基等离子体刻蚀；检测台阶高度、特征尺 寸、和腐蚀缺陷
e -
e
-

Glow discharge (plasma) Vacuum gauge
Ion sheath
e
Wafer Cathode electrode +
R
Flow of byproducts and process gases
Chamber wall Positive ion Radical chemical Vacuum line
Wafer Cassettes
Wafer Transfer System
Soft Bake
Cool Plate
Cool Plate
Hard Bake
Simplified Schematic of Dry Plasma Etcher
Gas distribution baffle Anode electrode Etchant gas entering gas inlet High-frequency energy RF coax cable Photon Electromagnetic field Free electron
Selective etching opens isolation regions in the epi layer.
+Ions
3
Photoresist
4
2
1
Nitride
Oxide n-well
4
h
p-well p- Epitaxial layer
STI trench
p+ Silicon substrate
Simplified Schematic of a Photolithography Processing Module
Load Station Vapor Prime Resist Coat Develop- Edge-Bead Rinse Removal Transfer Station Wafer Stepper (Alignment/Exposure System)
画出典型的流程图
2.
Give an overview of the six major process areas and the sort/test area in the wafer fab.
对6种主要工艺的应用和测试有大概的认识
3.
For each of the 14 CMOS manufacturing steps, describe its primary purpose.
Scanning ion beam
Photoresist Strip
Oxidation (Gate oxide)
Polysilicon Deposition
Polysilicon Mask and Etch
silicon nitride G ox S D S
Contact holes
Metal contacts G drain D S
CMOS Manufacturing Steps
1. 2. 3. 4. 5. 6. 7. Twin-well Implants 双阱注入 Shallow Trench Isolation 浅槽隔离
M-4 Passivation layer ILD-6
14
Bonding pad metal
ILD-5
n-well
Liner oxide
p-well p- Epitaxial layer
p+ Silicon substrate
Poly Gate Structure Process
18、去除氧化层：栅氧化前进行。
19、栅氧化层生长：完成后立即进行多晶硅淀积（~5000Ǻ） 20、第四层掩膜：光刻多晶硅栅；深紫外光刻；加抗反射涂层ARC；检测。 21、多晶硅栅刻蚀：先进的各向异性的等离子刻蚀机。
Gas inlet Process chamber Capacitivecoupled RF input
Chemical vapor deposition
Wafer Susceptor
Exhaust
Heat lamps
CVD cluster tool
Polish Bay in a Sub-micron Wafer Fab
p-well p- Epitaxial layer
p+ Silicon substrate
STI Formation
16、沟槽氧化抛光（CMP）： 17、氮化物去除：热磷酸
Planarization by chemical-mechanical polishing
1
STI oxide after polish 2 Nitride strip
STI Oxide Fill
14、沟槽衬垫氧化： 1000 C干氧，~150Ǻ； 15|、沟槽CVD氧化物填充：可用高速淀积。
Trench fill by chemical vapor deposition Oxide
2
Trench CVD oxide Nitride
1
n-well
Liner oxide
Via M-3 ILD-5 M-4 Passivation layer ILD-6
14
Bonding pad metal
13
ILD-4
12
M-2
ILD-3
11
M-1
ILD-2
10
ILD-1
金属2互连 13. Metal-3 to Pad Etch 金属3 压点形成 14. Parametric Testing 测试
Wafer Start
Unpatterned Wafer Thin Films Polish
Completed Wafer
Diffusion
Photo
Etch
Test/Sort