移位寄存器实验报告姓名：陈素学号：3120100621 专业：软件工程课程名称：逻辑与计算机设计基础实验同组学生姓名：张闻实验时间：y yyy-mm-dd 实验地点：紫金港东4-509 指导老师：一、实验目的和要求掌握移位寄存器的工作原理及设计方法掌握串、并数据转换的概念与方法了解序列信号在CPU控制器设计中的应用二、实验内容和原理2.1 实验原理带并行置入的移位寄存器移位寄存器：每来一个时钟脉冲，寄存器中的数据按顺序向左或向右移动一位必须采用主从触发器或边沿触发器不能采用电平触发器数据移动方式：左移、右移数据输入输出方式串行输入，串行输出串行输入，并行输出并行输入，串行输出串行输入的移位寄存器使用D触发器，可构成串行输入的移位寄存器2.2 标题<正文>带并行输入的右移移位寄存器数据输入移位寄存器的方式：串行输入、并行输入带并行输入的8位右移移位寄存器module shift_reg(clk, S, s_in, p_in, Q); input wire clk, S, s_in; input wire [7:0] p_in; output wire [7:0] Q; wire [7:0] D; wire nS;FD FDQ0(.C(clk), .D(D[0]), .Q(Q[0])), FDQ1(.C(clk), .D(D[1]), .Q(Q[1])), FDQ2(.C(clk), .D(D[2]), .Q(Q[2])), FDQ3(.C(clk), .D(D[3]), .Q(Q[3])), FDQ4(.C(clk), .D(D[4]), .Q(Q[4])), FDQ5(.C(clk), .D(D[5]), .Q(Q[5])), FDQ6(.C(clk), .D(D[6]), .Q(Q[6])), FDQ7(.C(clk), .D(D[7]), .Q(Q[7]));OR2 D0_L(.I0(L_0), .I1(R_0), .O(D[0])), D1_L(.I0(L_1), .I1(R_1), .O(D[1])), D2_L(.I0(L_2), .I1(R_2), .O(D[2])), D3_L(.I0(L_3), .I1(R_3), .O(D[3])), D4_L(.I0(L_4), .I1(R_4), .O(D[4])),串行输入SD5_L(.I0(L_5), .I1(R_5), .O(D[5])), D6_L(.I0(L_6), .I1(R_6), .O(D[6])), D7_L(.I0(L_7), .I1(R_7), .O(D[7]));并行－串行转换器 没有启动命令时并行－串行转换器ser_out并行输入par_in 移位输入7位并行-串行转换器ser_out并行输入par_in 移位输入7位并行-串行转换器2.1 实验内容用Verilog HDL语言，采用结构化描述方法设计一个8位带并行输入的右移移位寄存器。

编写该移位寄存器的代码模块shift_reg针对该模块，编写波形仿真输入代码进行波形仿真，并分析仿真结果是否正确设计16位带并行输入的右移移位寄存器。

2、增加到计算器模块中。

3、修改相关代码。

4、修改ucf文件。

5、下载并验证。

三、主要仪器设备必须采用编号样式，设备的数量和单位应对齐。

示范如下：1.xx开发板1套2.装有ISE的PC机1台四、操作方法与实验步骤修改TOP程序，添加移位寄存器Module top(input wire clk, input wire [7:0]btn_in, input wire[3:0]switch, output wire [11:0]anode, output wire [15:0]segment)reg [15:0] op1,op2;reg [15:0] display_num;wire [11:0] btn_out;wire [15:0] result,cnt;wire [31:0] display_num32b;wire clk_1s;wire [15:0] Q1,data_out;initial beginop1=16'b0011_0011_0011_0011;//3333op2=16'b0010_0010_0010_0010;//2222endpbdebounce p0(clk,btn_in[0],btn_out[0]);display m0(clk, display_num,anode[3:0], segment[7:0]); //display module display32bits m1(clk,display_num32b,anode[11:4],segment[15:8]); calculate_result m2(switch,op1, op2, result); //calculate resultcounter_1s m3(clk, clk_1s);couter_16reversible m4(clk_1s&btn_out[8],switch[4],cnt,Rc);shift_reg m6(btn_out[9], switch[8],switch[9] ,op1, Q1);regfile m7(btn_out[10],btn_out[11],switch[13:10], op2, data_out); always @(posedge btn_out[7]) op2[ 15: 12]<= op2[15: 12] + 4'd1; assign display_num32b = {op2,op1};//assign display_num=result;always @* begincase (switch[7:6])2'b00: display_num = result; //result2'b01: display_num = cnt;2'b10: display_num = Q1;2'b11: begin if (btn_out[10]==1) display_num = op2; else display_num = data_out;end endcaseendendmoduleRegfile--16程序模块1module regfile(wclk, rclk, address, data_in, data_out);input wire wclk,rclk;input wire [3:0]address;input wire [15:0]data_in;output wire [15:0]data_out;wire [15:0] Yi;wire [15:0] clk;assign clk[15:0] = {16{wclk}} & Yi;wire [15:0] regQ0,regQ1,regQ2,regQ3,regQ4,regQ5,regQ6,regQ7,regQ8,regQ9,regQ10,regQ11,regQ12,regQ13,regQ14,regQ15;decode_4_16 M0(address[3:0],wclk,Yi);//4-16译码器mux_16_1 M1(rclk, address[3:0],regQ0, regQ1, regQ2, regQ3,regQ4, regQ5, regQ6, regQ7,regQ8, regQ9, regQ10,regQ11,regQ12,regQ13,regQ14,regQ15,data_out);//16-1:多选一register16 R0(clk[0], data_in, regQ0),//clk=wclk&YiR1(clk[1], data_in, regQ1),R2(clk[2], data_in, regQ2),R3(clk[3], data_in, regQ3),R4(clk[4], data_in, regQ4),R5(clk[5], data_in, regQ5),R6(clk[6], data_in, regQ6),R7(clk[7], data_in, regQ7),R8(clk[8], data_in, regQ8),R9(clk[9], data_in, regQ9),R10(clk[10], data_in, regQ10),R11(clk[11], data_in, regQ11),R12(clk[12], data_in, regQ12),R13(clk[13], data_in, regQ13),R14(clk[14], data_in, regQ14),R15(clk[15], data_in, regQ15);endmodule4位4—16变量译码器程序模块module decode_4_16(address, wclk, Yi);input wire [3:0]address;input wire wclk;output reg [15:0]Yi;always @*beginif(wclk == 1'b1)case(address[3:0])4'b0000: Yi = 16'h0001;4'b0001: Yi = 16'h0002;4'b0010: Yi = 16'h0004;4'b0011: Yi = 16'h0008;4'b0100: Yi = 16'h0010;4'b0101: Yi = 16'h0020;4'b0110: Yi = 16'h0040;4'b0111: Yi = 16'h0080;4'b1000: Yi = 16'h0100;4'b1001: Yi = 16'h0200;4'b1010: Yi = 16'h0400;4'b1011: Yi = 16'h0800;4'b1100: Yi = 16'h1000;4'b1101: Yi = 16'h2000;4'b1110: Yi = 16'h4000;4'b1111: Yi = 16'h8000;endcaseelseYi = 16'h0000;endendmodule十六选一的数据选择器程序模块module mux_16_1(rclk, address, regQ0, regQ1, regQ2, regQ3, regQ4, regQ5, regQ6, regQ7, regQ8, regQ9, regQ10, regQ11, regQ12, regQ13, regQ14, regQ15,data_out);input wire rclk;input wire [3:0]address;input wire [15:0]regQ0, regQ1, regQ2, regQ3, regQ4, regQ5, regQ6, regQ7, regQ8,regQ9, regQ10, regQ11, regQ12, regQ13, regQ14, regQ15;output reg [15:0]data_out;always @(posedge rclk)begin//if(rclk == 1'b1)case (address[3:0])4'b0000: data_out = regQ0;4'b0001: data_out = regQ1;4'b0010: data_out = regQ2;4'b0011: data_out = regQ3;4'b0100: data_out = regQ4;4'b0101: data_out = regQ5;4'b0110: data_out = regQ6;4'b0111: data_out = regQ7;4'b1000: data_out = regQ8;4'b1001: data_out = regQ9;4'b1010: data_out = regQ10;4'b1011: data_out = regQ11;4'b1100: data_out = regQ12;4'b1101: data_out = regQ13;4'b1110: data_out = regQ14;4'b1111: data_out = regQ15;endcaseendendmodule16位D触发器程序模块module register16(cl, Di, Dot);//无R，D触发器input wire cl;input wire [15:0] Di;output reg [15:0] Dot;always @(posedge cl)Dot <= Di;endmodule16位全加器module adder_16bits(A, B, Ctr, S, Co);parameter size=16;input [15:1] A;input [15:1] B;input Ctr;output [11:1] S;output Co;wire[size-1:1] Ctemp;wire[size:1] Bo;assign Bo={16{Ctr}}^B;adder_1bit A1(.a(A[1]),.b(Bo[1]),.ci(Ctr),.s(S[1]),.co(Ctemp[1])), A2(A[2],Bo[2],Ctemp[1],S[2],Ctemp[2]),A3(A[3],Bo[3],Ctemp[2],S[3],Ctemp[3]),A4(A[4],Bo[4],Ctemp[3],S[4],Ctemp[4]),A5(A[5],Bo[5],Ctemp[4],S[5],Ctemp[5]),A6(A[6],Bo[6],Ctemp[5],S[6],Ctemp[6]),A7(A[7],Bo[7],Ctemp[6],S[7],Ctemp[7]),A8(A[8],Bo[8],Ctemp[7],S[8],Ctemp[8]),A9(A[9],Bo[9],Ctemp[8],S[9],Ctemp[9]),A10(A[10],Bo[10],Ctemp[9],S[10],Ctemp[10]),A11(A[11],Bo[11],Ctemp[10],S[11],Ctemp[11]),A12(A[12],Bo[12],Ctemp[11],S[12],Ctemp[12]),A13(A[13],Bo[13],Ctemp[12],S[13],Ctemp[13]),A14(A[14],Bo[14],Ctemp[13],S[14],Ctemp[14]),A15(A[15],Bo[15],Ctemp[14],S[15],Ctemp[15]),A16(A[16],Bo[16],Ctemp[15],S[16],Co);Endmodule一位全加器module adder_1bit(a, b, ci, s, co);// port declarationinput wire a,b,ci;output wire s,co;and (c1,a,b), (c2,b,ci), (c3,a,ci);xor (s1,a,b), (s,s1,ci);or (co,c1,c2,c3);endmodule拓展32位显示的程序module display32bits(clk,disp_num,digit_anode,segment);input clk;input [31:0] disp_num;output [7:0] digit_anode;output [7:0] segment;reg [7:0] digit_anode;reg [7:0] segment;reg [12:0] cnt=0;wire [31:0] disp_num;reg [3:0] num;always@(posedge clk)begincase(cnt[12:10])3'b000:begindigit_anode <= 8'b11111110;num <= disp_num[3:0];end3'b001:begindigit_anode <= 8'b11111101;num <= disp_num[7:4];end3'b010:begindigit_anode <= 8'b11111011;num <= disp_num[11:8];end3'b011:begindigit_anode <= 8'b11110111;num <= disp_num[15:12];end3'b100:begindigit_anode <= 8'b11101111;num <= disp_num[19:16];end3'b101:begindigit_anode <= 8'b11011111;num <= disp_num[23:20];end3'b110:begindigit_anode <= 8'b10111111;num <= disp_num[27:24];end3'b111:begindigit_anode <= 8'b01111111;num <= disp_num[31:28];endendcasecase(num)4'b0000:segment<=8'b11000000;4'b0001:segment<=8'b11111001;4'b0010:segment<=8'b10100100;4'b0011:segment<=8'b10110000;4'b0100:segment<=8'b10011001;4'b0101:segment<=8'b10010010;4'b0110:segment<=8'b10000010;4'b0111:segment<=8'b11111000;4'b1000:segment<=8'b10000000;4'b1001:segment<=8'b10010000;4'b1010:segment<=8'b10001000;4'b1011:segment<=8'b10000011;4'b1100:segment<=8'b11000110;4'b1101:segment<=8'b10100001;4'b1110:segment<=8'b10000110;4'b1111:segment<=8'b10001110;endcaseendalways@(posedge clk) begincnt<=cnt+1;endendmodule引脚代码NET "clk" LOC= "T9";NET "btn_in[0]" loc="E6";NET "btn_in[1]" loc="D5";NET "btn_in[2]" loc="C5";NET "btn_in[3]" loc="D6";NET "btn_in[4]" loc="C6";NET "btn_in[5]" loc="E7";NET "btn_in[6]" loc="C7";NET "btn_in[7]" loc="D7";NET "btn_in[8]" loc="M13";NET "btn_in[9]" loc="M14";NET "btn_in[10]" loc="L13";NET "btn_in[11]" loc="L14";NET "switch[0]" LOC="F12";NET "switch[1]" LOC="G12";NET "switch[2]" LOC="H14";NET "switch[3]" LOC="H13";NET "switch[4]" LOC="J14";NET "switch[5]" LOC="J13";NET "switch[6]" LOC="K14";NET "switch[7]" LOC="K13";NET "switch[8]" LOC="M10";NET "switch[9]" LOC="F3";NET "switch[10]" LOC="H4";NET "switch[11]" LOC="E4";NET "switch[12]" LOC="G5";NET "switch[13]" LOC="F4";NET "anode[0]" LOC="D14";NET "anode[1]" LOC="G14";NET "anode[2]" LOC="F14";NET "anode[3]" LOC="E13";NET "segment[0]" LOC="E14";NET "segment[1]" LOC="G13";NET "segment[2]" LOC="N15";NET "segment[3]" LOC="P15";NET "segment[4]" LOC="R16";NET "segment[5]" LOC="F13";NET "segment[6]" LOC="N16";NET "segment[7]" LOC="P16";NET "anode[4]" LOC = "B11" ; NET "anode[5]" LOC = "A10" ; NET "anode[6]" LOC = "B10" ; NET "anode[7]" LOC = "A9" ; NET "anode[8]" LOC = "A8" ; NET "anode[9]" LOC = "B8" ; NET "anode[10]" LOC = "A7" ; NET "anode[11]" LOC = "B7" ; NET "segment[8]" LOC = "C8" ; NET "segment[9]" LOC = "D8" ; NET "segment[10]" LOC = "C9" ; NET "segment[11]" LOC = "D10" ; NET "segment[12]" LOC = "A3" ; NET "segment[13]" LOC = "B4" ; NET "segment[14]" LOC = "A4" ; NET "segment[15]" LOC = "B5" ; module shift_reg(clk, S, s_in, p_in, Q); input wire clk, S, s_in;input wire [15:0] p_in;output wire [15:0] Q;wire D[15:0];wire nS;FD FDQ0(.C(clk), .D(D[0]), .Q(Q[0])), FDQ1(.C(clk), .D(D[1]), .Q(Q[1])), FDQ2(.C(clk), .D(D[2]), .Q(Q[2])), FDQ3(.C(clk), .D(D[3]), .Q(Q[3])), FDQ4(.C(clk), .D(D[4]), .Q(Q[4])), FDQ5(.C(clk), .D(D[5]), .Q(Q[5])), FDQ6(.C(clk), .D(D[6]), .Q(Q[6])), FDQ7(.C(clk), .D(D[7]), .Q(Q[7])), FDQ8(.C(clk), .D(D[8]), .Q(Q[8])), FDQ9(.C(clk), .D(D[9]), .Q(Q[9])), FDQ10(.C(clk), .D(D[10]), .Q(Q[10])), FDQ11(.C(clk), .D(D[11]), .Q(Q[11])), FDQ12(.C(clk), .D(D[12]), .Q(Q[12])), FDQ13(.C(clk), .D(D[13]), .Q(Q[13])), FDQ14(.C(clk), .D(D[14]), .Q(Q[14])), FDQ15(.C(clk), .D(D[15]), .Q(Q[15])); OR2 D0_L(.I0(L_0), .I1(R_0), .O(D[0])), D1_L(.I0(L_1), .I1(R_1), .O(D[1])),D2_L(.I0(L_2), .I1(R_2), .O(D[2])),D3_L(.I0(L_3), .I1(R_3), .O(D[3])),D4_L(.I0(L_4), .I1(R_4), .O(D[4])),D5_L(.I0(L_5), .I1(R_5), .O(D[5])),D6_L(.I0(L_6), .I1(R_6), .O(D[6])),D7_L(.I0(L_7), .I1(R_7), .O(D[7])),D8_L(.I0(L_8), .I1(R_8), .O(D[8])),D9_L(.I0(L_9), .I1(R_9), .O(D[9])),D10_L(.I0(L_10), .I1(R_10), .O(D[10])), D11_L(.I0(L_11), .I1(R_11), .O(D[11])), D12_L(.I0(L_12), .I1(R_12), .O(D[12])), D13_L(.I0(L_13), .I1(R_13), .O(D[13])),D14_L(.I0(L_14), .I1(R_14), .O(D[14])),D15_L(.I0(L_15), .I1(R_15), .O(D[15]));AND2 L0_L(.I0(Q[1]), .I1(nS), .O(L_0)),L1_L(.I0(Q[2]), .I1(nS), .O(L_1)),L2_L(.I0(Q[3]), .I1(nS), .O(L_2)),L3_L(.I0(Q[4]), .I1(nS), .O(L_3)),L4_L(.I0(Q[5]), .I1(nS), .O(L_4)),L5_L(.I0(Q[6]), .I1(nS), .O(L_5)),L6_L(.I0(Q[7]), .I1(nS), .O(L_6)),L7_L(.I0(Q[8]), .I1(nS), .O(L_7)),L8_L(.I0(Q[9]), .I1(nS), .O(L_8)),L9_L(.I0(Q[10]), .I1(nS), .O(L_9)),L10_L(.I0(Q[11]), .I1(nS), .O(L_10)),L11_L(.I0(Q[12]), .I1(nS), .O(L_11)),L12_L(.I0(Q[13]), .I1(nS), .O(L_12)),L13_L(.I0(Q[14]), .I1(nS), .O(L_13)),L14_L(.I0(Q[15]), .I1(nS), .O(L_14)),L15_L(.I0(s_in), .I1(nS), .O(L_15));AND2 R0_L(.I0(p_in[0]), .I1(S), .O(R_0)),R1_L(.I0(p_in[1]), .I1(S), .O(R_1)),R2_L(.I0(p_in[2]), .I1(S), .O(R_2)),R3_L(.I0(p_in[3]), .I1(S), .O(R_3)),R4_L(.I0(p_in[4]), .I1(S), .O(R_4)),R5_L(.I0(p_in[5]), .I1(S), .O(R_5)),R6_L(.I0(p_in[6]), .I1(S), .O(R_6)),R7_L(.I0(p_in[7]), .I1(S), .O(R_7)),R8_L(.I0(p_in[8]), .I1(S), .O(R_8)),R9_L(.I0(p_in[9]), .I1(S), .O(R_9)),R10_L(.I0(p_in[10]), .I1(S), .O(R_10)),R11_L(.I0(p_in[11]), .I1(S), .O(R_11)),R12_L(.I0(p_in[12]), .I1(S), .O(R_12)),R13_L(.I0(p_in[13]), .I1(S), .O(R_13)),R14_L(.I0(p_in[14]), .I1(S), .O(R_14)),R15_L(.I0(p_in[15]), .I1(S), .O(R_15));INV nS_L(.I(S), .O(nS));endmodule报告的第二、三、四部分是重点，请认真书写。