问答：Point out design objects in the figure such as :design, cell, reference, port, pin, net, then write a command to set 5 to net ADesign: topReference: ADD DFFCell: U1 U2Port: A B clk sumPin: A B D QNet: A B SINSet_load 5 [get_nets A]why do we not choose to operate all our digital circuits at these low supply voltages? 答：1）不加区分地降低电源电压虽然对减少能耗能正面影响，但它绝对会使门的延时加大 2）一旦电源电压和本征电压（阈值电压）变得可比拟，DC特性对器件参数（如晶体管阈值）的变化就变得越来越敏感3）降低电源电压意味着减少信号摆幅。

虽然这通常可以帮助减少系统的内部噪声（如串扰引起的噪声），但它也使设计对并不减少的外部噪声源更加敏感）问道题：1.CMOS静态电路中，上拉网络为什么用PMOS,下拉网络为什么用NMOS管2.什么是亚阈值电流，当减少VT时，V GS =0时的亚阈值电流是增加还是减少？3.什么是速度饱和效应4.CMOS电压越低，功耗就越少？是不是数字电路电源电压越低越好，为什么？5.如何减少门的传输延迟？ P2036.CMOS电路中有哪些类型的功耗？7.什么是衬垫偏置效应。

8.gate-to-channel capacitance C GC,包括哪些部分VirSim有哪几类窗口3-6. Given the data in Table 0.1 for a short channel NMOS transistor withV DSAT = 0.6 V and k′=100 µA/V2, calculate V T0, γ, λ, 2|φf|, and W / L:解答:对于短沟道器件：2'min min [()](1)2DGS T DS V WI k V V V V L λ=--+ min min[(),,]GS T DS DSAT V V V V V =-在选择公式的时候，首先要确定工作区域，表格中的所有V DS 均大于V DSAT ，所以不可能工作在线性区域。

如果工作在饱和区域则： V T 应该满足 : V GS -V T <V DSAT 2-V T <0.6 1.4<V T这是不可能的，所以可以假设所有的数据都是工作在速度饱和区域 所以：2'[()](1)2DSAT D GS t DSAT DS V WI k V V V V L λ=--+由 1&22'00.6[(2.5)0.6](1 1.8)18122D W I k Vt L λ=--+=2'00.6[(2)0.6](1 1.8)12972D W I k Vt L λ=--+= 20200.6(2.5)0.61812212970.6(2)0.62Vt Vt --=--0.44VtV=(01.4Vt V<) 所以 1,2,3是在速度饱和区由 2&312971 1.813611 2.5λλ+=+10.08V λ-=由 2&4 1297/1146=[（2-Vt0）x0.6-o.62/2]/[(2-Vt)x0.6-0.62/2] Vt=0.587V由 2 &5 Vt=0.691V这两个值都满足 Vt<1.4, 所以表中的数据都是工作的速度饱和状态0(22)SB f fVt Vt V γφφ=++-由4 &5 和 00.44Vt V=可以计算出20.6f Vφ= 和1/20.3V γ=2'1297[()]2DSAT DGS t DSAT V WI A k V V V L μ==-- 得到 W/L=1.53-7 Giv en Table 0.2 ,the goal is to derive the important device parametersfromthese data points. As the measured transistor is processed in a deep-submciron technology, the‘unified model ’ holds. From the material constants, we also could determine that the saturation voltage V DSAT equals -1V. You may also assume that -2ΦF = -0.6V.NOTE: The parameter values on Table 3.3 do NOT hold for this problem. a. Is the measured transistor a PMOS or an NMOS device? Explain your answer.b. Determine the value of VT0.c. Determine γ.d. Determine λ.e. Given the obtained answers, determine for each of the measurements the operation region of the transistor (choose from cutoff, resistive, saturated, and velocity saturated ). Annotateyour finding in the right-most column of the above.解答:a) 这是 PMOS 器件 b) 2'min min[()](1)2D GS T DS V WI kV V V V Lλ=--+比较各表中(),,GS T DS DSAT V V V V -的值知道1，4为工作在速度饱和状态由 1&42'[()](1)2DSAT D GS t DSAT DS V WI k V V V V L λ=--+2'01[( 2.5)(1)](1*( 2.5))84.3752D W I k Vt L λ=----+-=-2'01[( 2.0)(1)](1*( 2.5))56.252D W I k Vt L λ=----+-=-20201( 2.5)(1)84.375256.251( 2.0)(1)2Vt Vt -----=-----Vt 0=0.5Vc) 由 1&5和上面求出的Vt0的值: 1，5工作在速度饱和区域 则：（-84.375）/(-72.0)=[（-2.5-Vt0）*(-1)-12/2]/[(-2.5-Vt)*(-1)-12/2]求出Vt ，代入下面公式：0Vt Vt γ=+-求出：γ=0.538V 1/2d)由 1&6，因为1，6均工作在速度饱和区域:84.3751( 2.5)80.6251( 1.5)λλ-+-=-+-λ=0.05V -1e)1-vel. Sat, 2-cutoff, 3-saturation , 4-5-6 vel. Sat, 7-linear3-8 An NMOS device is plugged into the test configuration shown below in Figure0.4. The input V in =2V. The current source draws a constant current of 50 µA. R is a variableresistor that can assume values between 10k Ω and 30 k Ω. Transistor M1 experiences short channel effects and has following transistor parameters: k ’ = 110*10-6 V/A2, V T = 0.4 ,and V DSAT = 0.6V. The transistor has a W/L = 2.5µ/0.25µ. For simplicity body effect andchannel length modulation can be neglected. i.e λ=0, γ=0. .a. When R =10k Ω find the operation region, V D and V S .b. When R= 30k Ω again determine the operation region V D , V Sc. For the case of R = 10k Ω, would V S increase or decrease if λ ≠ 0. Explain qualitatively解答:1)当 R=10k, V D =V DD -IRV D =2.5-50x10-6x104=2.5-0.5=2V假设器件工作在饱和区 ( 需要以后验证)则：2'()50D GS t WI K V V A Lμ=-= GS t V V -=0.3V 所以 V GS =0.3+0.4=0.7VV S =2-0.7=1.3VVmin=min(V GS -Vt, V DSAT , V DS )=min(0.3,0.6,0.7)=V GS -Vt 所以是饱和区V D =2VV S =1.3V saturation operationb) V D =2.5-30x103x50x10-6=2.5-1.5=1V assume linear op:2'()]502DS DGS t DS V WI K V V V A L μ=--=26(1)1101010(20.4)(1)]502S S S V V V Aμ--⨯⨯----= 0.93S V V=Min(V GS -V T ,V DS ,V DSAT )=min((1-0.93-0.4).0.07,0)=V DS SO linearc) increas e , R = 10k Ω2'()(1)D GS t DS WI K V V V Lλ=-+ R 变化，则V D 必须变化以保持电流稳定，(1)DS V λ+试图增加电流，而为了恒定电流值，V GS 必须减小，即V S 必须增加 1、（10）P137Assume an inverter in the generic 0.25 mm CMOS technology designed with a PMOS/NMOS ratio of 3.4 and with the NMOS transistor minimum size (W = 0.375 mm, L = 0.25 mm, W /L =1.5). V M = 1.25 V, please compute V IL , V IH , N ML , N MH . the processparametersispresentedintable1()(/2)(1)DM n DSATnin Tn DSATn n out IV k VV V V V λ=--+由此可以得到 V IL , V IH , NM L , NM H :因为V IH =V M -V M /g , V IL =V M +(V DD -V M )/g NM H =V DD -V IH , NM L =V IL V IL =1.2V, V IH =1.3V, NM L =NM H =1.25.3、For the inverter of Figure 1 and an output load of 3 pF ，at Vout=2.5V, I DVsat =0.439mA, at Vout=1.25V, I D vsat=0.41mAfig 1a. Calculate t plh , t phl , and t p .b. Are the rising and falling delays equal? Why or why not? 解答：t pLH =0.69R L C L = 155 nsec.对于 tp HL :首先计算 R on for V out at 2.5V and 1.25V. 因为 Vout=2.5V, I DVsat =0.439mA 所以 Ron= 5695 当 Vout=1.25V, IDvsat=0.41m 所以Ron= 3049.这样， Vout=2.5Vand Vout=1.25V 之间的平均电阻 Raverage=4.372k t pLH =0.69RaverageC L =9.05nsec. t p =av{t pLH , t pHL }=82.0nsecb. Are the rising and falling delays equal? Why or why not? Solutiont pLH >> t pHL 因为 R L =75k 远大于有效线性电阻 effective linearized on-resistance of M1.5-5 The next figure shows two implementations of MOS inverters. The first inverter uses onlyNMOS transistors. Calculate V OH , V OL , V M for each case. 有的参数参考表1解答：电路 A.V OH: 当 M1关掉， M2 的阈值是:当下面条件满足的时候，M2将关闭:所以 V OUT=V OH=1.765VV OL: 假设V IN=V DD=2.5V.我们期望 V OUT为低, 因此我们可以假设M2工作在速度饱和区，而M1工作在线性区域.因为 I D1= I D2 , 所以 V OUT=V OL=0.263V, 假设成立V M: 当V M=V IN=V OUT.假设两晶体管均工作在速度饱和区域, 我们得到下面两个方程:设 I D1=I D2, 得到 V M=1.269V电路 B.当 V IN=0V, NMOS 关掉，PMOS 打开，并把V OUT拉到VDD, so V OH=2.5. 同样, 当 V IN=2.5V, the PMOS关掉，NMOS 把 V OUT拉到地, 所以V OL=0V.为了计算 V M： V M=V IN=V OUT.假设两晶体管均工作在速度饱和区域，可以得到下面两组方程.设 I D3+ I D2 =0 ,可以得到r V M = 1.095V.所以假设两晶体管均工作在速度饱和区域是正确的.5-7Consider the circuit in Figure 5.5. Device M1 is a standard NMOS device. Device M2 has allthe same properties as M1, except that its device threshold voltage is negative and。