1.041HDLVerilog HDL()2004.8.3yyyy/mm/ddVerilog HDL2004.8.31.002004-08-16241285 ..............................................................274.8 case . (25)4.7 (25)4.6.6 (25)4.6.5 (24)4.6.4 (23)4.6.3 (22)4.6.2 (21)4.6.1 (21)4.6 (20)4.5.2 (20)4.5.1 (20)4.5 (18)4.4.2 (18)4.4.1 (18)4.4 (18)4.3 (17)4.2 (17)4.1.3 (17)4.1.2 (17)4.1.1 (17)4.1 (17)4 Verilog HDL ....................................................163.3.4 .. (15)3.3.3 (14)3.3.2 (12)3.3.1 (12)3.3 (11)3.2 (11)3.1.3 (10)3.1.2 (9)3.1.1 (9)3.1 (9)3 Verilog HDL .....................................................72.4.2 . (7)2.4.1 (7)2.4 Verilog HDL (6)2.3 (6)2.2 (5)2.1 (5)2 HDL ......................................................51 ...................................................................Verilog HDL 2004-08-163414010 A Verilog ...................................................399 ..................................................................398 ..............................................................377.4 ...................................................367.3 ......................................................357.2 ........................................................357.1 .............................................................357 ..............................................................346.3 .................................................346.2 ......................................................346.1 ......................................................346 ............................................................315.4 .................................................295.3 ........................................................285.2 ..........................................................285.1 ......................................................Verilog HDL 2004-08-16441Verilog HDLVerilog HDL HDLVerilog HDL Verilog HDL2000.7J.BhaskerVerilog HDLAMBIT Design System QuisckReferencefor Verilog HDL1VHDL Verilog HDL ASIC Verilog HDL VHDL ASIC/FPGAASIC/FPGA ASIC HDLVerilog HDLVerilog HDLVerilogTestBench2 HDLVerilog HDL 2004-08-16541Verilog HDL2.11. C MATLAB2. RTL3.4.RTL2.2CAE CAE74ASIC ASICEDAEDAHDL Hardware Description LanguageEDA ASIC FPGA274"& ""C = A & B"2"and "IEEE VHDL Verilog HDL2.3ASIC2004-08-16641Verilog HDL1 TOP-DOWN2.4 Verilog HDLVerilog HDL RTL2.4.1Verilog HDL 1983 Gateway Design AutomationVerilog HDLVerilog HDL 1990 Open Verilog International O V IVerilog 1992 OVI Verilog OVI IEEEVerilog 1995 IEEE IEEE Std13641995 Verilog2.4.2Verilog HDL Verilog HDL1.Verilog HDLVerilog HDLVerilog HDLVerilog CVerilog HDL Verilog 2004-08-16741Verilog HDLHDL ,2.listy and or nandy pmos nmosy------y Verilog HDLyyy Verilog HDL I E E Ey Verilog E D Ay RT Lyyy Verilog HDLy Verilog HDL RT LyyVerilog HDL22004-08-16841Verilog HDL3 Verilog HDLRAMVerilog HDL HDLVerilog HDL3.1module VerilogALU CPU3.1.1Verilog HDL[1]module addr (a, b, cin, count, sum);input [2:0] a;input [2:0] b;input cin;output count;output [2:0] sum;assign {count,sum} = a +b + cin;endmodule3module endmodule[2]module compare equal a binput[1:0] a,b; // declare the input signal ;output equare ; // declare the output signal;assign equare = (a == b) ? 1:0 ;/ * if a = b , output 1, otherwise 0*/endmodule2004-08-16941Verilog HDL/* .... */ // ...[3]module mytri (din, d_en, d_out);input din;input d_en;output d_out;// -- Enter your statements here -- //assign d_out = d_en ? din :'bz;endmodulemodule trist (din, d_en, d_out);input din;input d_en;output d_out;// -- statements here -- //mytri u_mytri(din,d_en,d_out);endmodulemytri trist mytri mytri trist tristu_mytri3.1.2module1module endmoduleTop-Down 3.3.1[3] 2module addr (a, b, cin, count, sum); module addrpinI/OI/O input [2:0] a; input [2:0] b;input cin; output count; input output inout [n:0]2004-08-161041assign d_out = d_en ? din :'bz;mytri u_mytri(din,d_en,d_out);HDLassign always34Verilog HDL5endmodule3.1.31.module module_name (port1, port2, ......) ;// D e c l a r a t i o n s :input, output, inout,reg, wire, parameter,function, task, . . .//S t a t e m e n t s :Initial statementAlways statementModule instantiationGate instantiationContinuous assignmentendmoduleModule instantiation 2.3.2HDLassign # 2 B = AB2A3Verilog HDL`timescale 1ns /100ps'timescale Verilog HDL 1ns 1ns 100ps 100ps #2 2nsVerilog HDL IEEE3.3HDL3.3.1HDLVerilog HDL and xor[1]4module FA_struct (A, B, Cin, Sum, Count);input A;input B;input Cin;output Sum;output Count;wire S1, T1, T2, T3;// -- statements -- //xor x1 (S1, A, B);xor x2 (Sum, S1, Cin);and A1 (T3, A, B );and A2 (T2, B, Cin);and A3 (T1, A, Cin);or O1 (Cout, T1, T2, T3 );endmoduleS1T1T2T3xor and or Verilog HDL xor x1 (S1, A, B)xor xor x1S1A B A B S1[2]5module Four_bit_FA (FA, FB, FCin, FSum, FCout ) ;parameter SIZE = 2;input [SIZE:1] FA;input [SIZE:1] FB;input FCin;output [SIZE:1] FSum;output FCout;wire FTemp;FA_struct FA1(.A (FA[1]),.B (FB[1]),.Cin (FCin) ,.Sum (FSum[1]),.Cout (Ftemp));FA_struct FA2(.A (FA[2]),.B (FB[2]),.Cin (FTemp) ,.Sum (FSum[2]),.Cout (FCount ));endmoduleFour_bit_FA FA_struct FA_struct.A FA[2].AA Awire Ftemp3.3.2assign [delay] net_name = expression;assign #2 A = BHDL&)|6`timescale 1ns/100psmodule FA_flow(A,B,Cin,Sum,Count)input A,B,Cin;output Sum, Count;wire S1,T1,T2,T3;assign # 2 S1 = A ^ B;assign # 2 Sum = S1 ^ Cin;assign #2 T3 = A & B;assign #2 T1 = A & Cin;assign #2 T2 = B & Cin ;endmoduleassignA S1T3T1 S1Sum3.3.3initial always+-initial always[1]module FA_behav1(A, B, Cin, Sum, Cout );input A,B,Cin;output Sum,Cout;reg Sum, Cout;reg T1,T2,T3;always@ ( A or B or Cin )beginSum = (A ^ B) ^ Cin ;T1 = A & Cin;T2 = B & Cin ;T3 = A & B;Cout = (T1| T2) | T3;endendmodule1always initial reg2always always3always 04begin end[2]module FA_behav2(A, B, Cin, Sum, Cout );input A,B,Cin;output Sum,Cout;reg Sum, Cout;always@ ( A or B or Cin )begin{Count Sum} = A + B + Cin ;endendmodule2"+" {Count Sum}1bit Sum Count3.3.4bitFour_bit_FA)FA4 Verilog HDLVerilog HDLIF4.14.1.1( identifier Verilog HDL ( identifier )$_()CountCOUNT //CountR56_68FIVE$4.1.2Verilog HDL Aalways ()ALWAYS()4.1.3Verilog1 Sum CPU_addr23Clk Clk_50Clk_CPU_n Enable_n4 Rst567SIZE4.2Verilog HDL "/*""*/"/* statement1statement2.. ...statementn */n// //4.3Verilog HDLVerilog HDLinput A input Binput Ainput Btable4.4Verilog HDL4.4.1Verilog HDL00""11""XZz 0 0"z ""x "x z 0x1z 0X1Z Verilog HDL4.4.2Verilog HDL_1.1)2)A."+"""32 321515B.[size ] 'base valuesize base o O b B d Dh H value base x za f5 'O37 5 111114'D2 4 00114'B1x_01 47'Hx7x(x), xxxxxxx4'hZ 4 z(z) , zzzz4'd-48'h 2A3' b 001 ` b(2+3)'b10x z 4 x z 3 x z1 x z'o7219'h AF80 xz x z10'b100 , 000000001010'bx0x1x , x x x x x x x 0 x 13 ' b1001 _ 0011 3'b0115'H0FFF 5'H1F2."INTERNAL ERROR"" REACHED>HERE "8 ASCII 8 ASCII"INTERNAL ERROR "8 * 1 4r e g [1: 8*14] Message;. . .Message = "INTERNAL ERROR"4.5Verilog HDL(net type) reg type4.5.11.wire triwire triA BX1S1X2X1assign assign A = B ^ Cwire ZwireA B SUM wire2.tri4.5.21.reg D ROMreg always regregreg [msb: lsb] reg1, reg2, . . . r e g N;msb lsb1reg [3:0] Sat; // S a t 4reg Cnt; //1reg [1:32] Kisp, Pisp, Lisp ;reg A.....A = -1....A1111A152.Dreg [10] Dout.....always@(posedge Clk)Dout<= Din;....28RAMreg [70] Mem[01]28RAM.....Mem[0] = 'h 55Mem[1] = 'haa....3.[70]4.64.6.1"+""-""*"1.reg [3:0] Arc, Bar, Crt;reg [5:0] Frx;. . .Arc = Bar + Crt;Frx = Bar + Crt;Bar Crt A rc 4Frx Frx Bat Crt 6 Frx [ 4 ]Verilog HDLwire [4:1] Box, Drt;wire [5:1] Cfg;wire [6:1] Peg;wire [8:1] Adt;. . .assign Adt = (Box + Cfg) + (Drt + Peg) ;6 88 Box Cfg 82.4.6.2?>?<?>=?<== ==1 0 X Z X23 > 4552< 8'hxFFx0 'b1000 > = 'b01110'b01000 > = 'b01110x z xData = 'b11x0;Addr = 'b11x0;Data = = Addr x4.6.3&& ()|| ()()12 ....010 1 , Crd = 'b0; //0Dgs = 'b1; //1Crd && Dgs 0 ()Crd || Dgs 1 ()D g s 0 ()&&)1xx x X/Zx 101x 000(X/Z1&&2x1x x/z 1111x 100x/z10||4.6.4?~?&?| ?^?~ ^, ^ ~7,A = 'b0110;B = 'b0100;A |B 0 1 1 0A &B 0 1 0 0, 0 ,'b0110 ^ 'b10000:'b00110 ^ 'b10000' b 1 0 11 04.6.5cond_expr ? expr1 : expr2cond_expr ( 1 )expr1 cond_expr (0 )expr2 cond_expr x z expr1 expr2 0 0 0 1 1 1 x:wire [2:0] Student = Marks > 18 ? Grade_A : Grade_C;Marks > 18; , Grade_A Student; Marks < =18, Grade_C Student4.6.6{expr1, expr2, . . .exprN}wire [7:0] Dbus;assign Dbus [7:4] = {Dbus [0], Dbus [1], Dbus[2], Dbus[ 3 ] } ;/ / 4 4assign Dbus = {Dbus [3:0], Dbus [ 7 : 4 ] } ;/ / 4 4, ,{Dbus,5} / /4.7ifif(condition_1)procedural_statement_1{else if(condition_2)procedural_statement_2}{elseprocedural_statement_3}condition_1 procedural_statement_1 condition_1 0 x z procedural_statement_1 elseif(Sum < 60)beginGrade = C;Total_C = Total _c + 1;endelse if(Sum < 75)beginGrade = B;Total_B = Total_B + 1;endelsebeginGrade = A;Total_A = Total_A + 1;endif - if - elseif(C l k)if(R e s e t)Q = 0;elseQ = D;else if? if (Clk)if (Reset)? Verilog HDL else else ifelse ififif(Sum < 100)Sum = Sum + 10;if(Nickel_In)Deposit = 5;elseif (Dime_In)Deposit = 10;else if(Quarter_In)Deposit = 25;elseDeposit = ERROR;12if - if begin --- endif(C l k)beginif(R e s e t)Q = 0;elseQ = D;end3if if elseASICif TQ = Delse T1 D Q T0else Q4.8 casecasecase(case_expr)case_item_expr{ ,case_item_expr} :procedural_statement. . .. . .[default:procedural_statement]endcasecase case_expr1case (HEX)4'b0001 :LED = 7'b1111001;// 14'b0010:LED = 7'b0100100;// 24'b0011:LED = 7'b0110000;// 34'b0100:LED = 7'b0011001;// 44'b0101:LED = 7'b0010010;// 54'b0110:LED = 7'b0000010;// 64'b0111:LED = 7'b1111000;// 74'b1000:LED = 7'b0000000;// 84'b1001:LED = 7'b0010000;// 94'b1010:LED = 7'b0001000;// A4'b1011:LED = 7'b0000011;// B4'b1100:LED = 7'b1000110;// C4'b1101:LED = 7'b0100001;// D4'b1110:LED = 7'b0000110;// E4'b1111:LED = 7'b0001110;// Fdefault :LED = 7'b1000000;// 0endcasecase53.3.15.1module module module module_name (port_list) ;Declarations_and_StatementsendmoduleVerilog HDL and xor 3.3.1xorFPGAport_list5.2wireregmodule Micro (PC, Instr, NextAddr );/ /input [3:1] PC;output [1:8] Instr;inout [16:1] NextAddr;/ /wire [16:1] NextAddr; // wire16reg [1:8] Instr; / /Instr reg always initial. . .endmodule5.31.module_name instance_name(port_associations) ;port_expr / /.PortName (port_expr) / /[1]....module and C A Binput A Boutput C...and A1 (T3, A, B ); //T3C A A B Band A2//.C and T3 .C T3.A A.B B....port_expr1) reg net .C T3T3wire2) .C D[0]C D0bit3) .Bus Din[54]4) .Addr{ A1A2[10]}5) .A wire Zire = 0 2.DFF d1 (.Q(QS),.Qbar ( ),.Data (D ) ,.Preset ( ), //.Clock (CK)); //Z3.module Child (Pba, Ppy) ;input [5:0] Pba;output [2:0] Ppy;. . .endmodulemodule Top;wire [1:2] Bdl;wire [2:6] M p r;Child C1 (Bdl, Mpr) ;endmoduleChild Bdl[2]Pba[ 0 ]Bdl[1] Pba[ 1 ]Pba[5]Pba[4]Pba[3]z Mpr[6]Ppy[0]Mpr[5] Ppy[1]Mpr[4] Ppy[2 ]85.4module module verilog HDLHDL2LED49CNT_BCD CNT_BCD.v AND2CNT_4b HEX2LED10CNT_BCD CNT_BCD.vmodule CNT_BCD (BCD_A,BCD_B,BCD_C,BCD_D,CLK,GATE,RESET) ;// ------------ Port declarations --------- //input CLK;input GATE;input RESET;output [3:0] BCD_A;output [3:0] BCD_B;output [3:0] BCD_C;output [3:0] BCD_D;wire CLK;wire GATE;wire RESET;wire [3:0] BCD_A;wire [3:0] BCD_B;wire [3:0] BCD_C;wire [3:0] BCD_D;// ----------- Signal declarations -------- //wire NET104;wire NET116;wire NET124;wire NET132;wire NET80;wire NET92;// -------- Component instantiations -------//CNT_4b U0(.CLK(CLK),.ENABLE(GATE),.FULL(NET80),.Q(BCD_A),.RESET(RESET));CNT_4b U1(.CLK(CLK),.ENABLE(NET116),.FULL(NET92),.Q(BCD_B),.RESET(RESET) );CNT_4b U2(.CLK(CLK),.ENABLE(NET124),.FULL(NET104),.Q(BCD_C),.RESET(RESET) );CNT_4b U3(.CLK(CLK),.ENABLE(NET132),.Q(BCD_D),.RESET(RESET) );AND2 U4(.A0(NET80),.A1(GATE),.Y(NET116));AND2 U5(.A0(NET92),.A1(NET116),.Y(NET124));AND2 U6(.A0(NET104),.A1(NET124),.Y(NET132));endmoduleAND263.3.26.1(assign )assign net_type =wirewire [3:0] Z, Preset, Clear; //assign Z = Preset & Clear; //wire Cout, C i n ;wire [3:0] Sum, A, B;. . .assign {Cout, Sum} = A + B + Cin;assign Mux = (S = = 3)? D : 'bz;126.2"="assign6.3AND2AND2AND2.vmodule AND2 (A0, A1, Y);input A0;input A1;output Y;wire A0;wire A1;wire Y;// add your code hereassign Y = A0 & A1;endmodule73.3.37.1initial always7.2Verilog HDL (begin . . . end)begin[ :block_id{declarations} ]procedural_statement ( s )end/ / :begin#2 Stream = 1;#5 Stream = 0;#3 Stream = 1;#4 Stream = 0;#2 Stream = 1;#5 Stream = 0;end1 0 1 121 17 ( 5 ) 12 0117.3Verilog HDL initial alwaysbegin ....end1. initialinitial 0initial[timing_control] procedural_statementprocedural_statementprocedural_assignment (blocking or non-blocking ) / // /procedural_continuous_assignmentconditional_statementcase_statementloop_statementwait_statementdisable_statementevent_triggertask_enable (user or system)initialbegin#2 Stream = 1;#5 Stream = 0;#3 Stream = 1;#4 Stream = 0;#2 Stream = 1;#5 Stream = 0;end2.alwaysalways initialalways[1]initialClk = 0always#5 Clk = ~Clkalways Clk 0 10[2] Dalways @ ( posedge Clk or posedge Rst )beginif RstQ <= `b 0;elseQ <= D;alwaysRst 1 Q D Q@[3] 2always @( sel a bC = sel ? a bsel a b always sel 1 Ca b mux1alwaysa b3sel2"="3"<=" Q = D7.4HEX2LED CNT_4bCNT_4b CNT_4b.vmodule CNT_4b (CLK, ENABLE, RESET, FULL, Q);input CLK;input ENABLE;input RESET;output FULL;output [3:0] Q;wire CLK;wire ENABLE;wire RESET;wire FULL;wire [3:0] Q;// add your declarations herereg [3:0] Qint;always @(posedge RESET or posedge CLK)beginif (RESET)Qint = 4'b0000;else if (ENABLE)beginif (Qint == 9)Qint = 4'b0000;elseQint = Qint + 4'b1;endendassign Q = Qint;assign FULL = (Qint == 9) ? 1'b1 : 1'b0;endmodule10HEX2LED HEX2LED.vmodule HEX2LED (HEX, LED);input [3:0] HEX;output [6:0] LED;wire [3:0] HEX;reg [6:0] LED;// add your declarations herealways @(HEX)begincase (HEX)4'b0001 :LED = 7'b1111001;// 14'b0010:LED = 7'b0100100;// 24'b0011:LED = 7'b0110000;// 34'b0100:LED = 7'b0011001;// 44'b0101:LED = 7'b0010010;// 54'b0110:LED = 7'b0000010;// 64'b0111:LED = 7'b1111000;// 74'b1000:LED = 7'b0000000;// 84'b1001:LED = 7'b0010000;// 94'b1010:LED = 7'b0001000;// A4'b1011:LED = 7'b0000011;// B4'b1100:LED = 7'b1000110;// C4'b1101:LED = 7'b0100001;// D4'b1110:LED = 7'b0000110;// E4'b1111:LED = 7'b0001110;// Fdefault :LED = 7'b1000000;// 0endcaseendendmodule10 744HDL HDL8`define `include task912HDL 434CPU Top-Down5D Reg8 Din Qout8Clk Rst8moduleDQDCKR12 D symbol6HDL7.A A A891011Verilog HDL12 5 'O374'D28'h 2A7'Hx5'H7F1314initial always20ns1Rst 040ns 1010 A Verilogalways and assign begin buf buf if0bufif1case casex casez cmosdeassign default defparam disable edge else end endcase endmodule endfunction endprimitive endspecify endtable endtask eventfor force forever fork function highz0highz1 if ifnone initial inout input integer join large macrmodule medium module nand negedge nmos nor not notif0notif1or output parameter pmos posedge primitive pull0pull1pullup pulldownrcmos real realtime reg release repeat rnmos rpmos rtran rtranif0Verilog HDLrtranif1scalared small specify specparam strong0strong1supply0supply1 table task time trantranif0tranif1tri tri0tri1triand triortrireg vectored wait wand weak0weak1while wire wor xnor xor 2004-08-164141。