E D A基础总结综述部分1.EDA的中文全称为电子设计自动化，英文全名为Electronic Design Automation。

2.EDA平台常用的两种输入电路的方法是：电路原理图输入法、HDL输入法。

3.EDA平台工作流程：电路输入、综合优化、功能仿真、布局布线、门级仿真。

数字电路部分1.EDA中常用的仿真语言为Verilog和VHDL。

2.VHDL其英文全名为VHSIC Hardware Description Language，而VHSIC则是Very HighSpeed Intergeraterd Circuit的缩写词，意为甚高速集成电路，故VHDL其准确的中文译名为甚高速集成电路的硬件描述语言。

3.Verilog HDL其英文全名为Verilog Hardware Decription Language，HDL中文译名为硬件描述语言。

4.Verilog和VHDL的比较共同点：能形式化地抽象表示电路的行为和结构；支持逻辑设计中层次与范围的描述；可借用高级语言的精巧结构来简化电路行为的描述；具有电路仿真与验证机制以保证设计的正确性；支持电路描述由高层到低层的综合转换；硬件描述与实现工艺无关；便于文档管理；易于理解和设计重用。

不同点：Verilog在系统级抽象方面略差，VHDL在门级开关电路方面略差。

5.软核、固核和硬核软核：功能经过验证的、可综合的、实现后电路结构总门数在5000门以上的Verilog 模型。

固核：在某一种现场可编程门列器件上实现的经验证是正确的，且总门数在5000门以上的电路结构编码文件。

硬核：在某一种专用集成电路工艺的器件上实现的，经验证是正确的，且总门数在5000门以上的电路结构版图掩膜。

6.自顶向下（Top Down）设计7.自底向上（Down Top）设计8.名词解释：ASIC：Application Specific Integrated Circuit，专用集成电路。

FPGA：Field Programmable Gate Array，现场可编程门阵列。

PLD：Programmable Logic Device，可编程逻辑器件。

Verilog编程题：数据比较器（2位）//数据比较器module compare (equal, a, b);input a,b;output equal;reg equal;always @(a or b)if (a == b)equal = 1;elseequal = 0;endmodule//数据比较器测试代码`timescale 1ns/1ns`include "./1-1.v"module t;reg a,b;wire equal;initialbegina=0;b=0;#100 a=0; b=1;#100 a=1; b=1;#100 a=1; b=0;#100 a=0; b=0;#100 $stop;endcompare m(.equal(equal), .a(a), .b(b)); endmodule数据比较器（8位）module compare8(equal, a, b);input [7:0]a, b;output equal;reg equal;always @(a or b)if (a > b)beginequal = 1;endelsebeginequal = 0;endendmodule分频器module half_clk(reset, clk_in, clk_out); input clk_in, reset;output clk_out;reg clk_out;always @(posedge clk_in)beginif(!reset) clk_out = 0;else clk_out = ~clk_out;endendmodule10M时钟分频为500Kmodule fdivision (RESET, MB, KB);input MB, RESET;output KB;reg KB;reg [7:0] j;always @(posedge MB)if (!RESET)beginKB <= 0;j <= 0;endelsebeginif (j == 19)begin j <= 0;KB <= ~KB;endelsej <= j+1;endendmodule译码电路`define plus 3'd0`define minus 3'd1`define band 3'd2`define bor 3'd3`define unegate 3'd4module alu(out, opcode, a, b);output[7:0] out;reg[7:0] out;input[2:0] opcode;input[7:0] a,b;always @(opcode or a or b)begincase(opcode)`plus: out = a + b;`minus: out = a - b;`band: out = a & b;`bor: out = a | b;`unegate: out = ~a;default: out = 8'hx;endcaseendendmodule八路数据选择器module selecting8(addr, in1, in2, in3, in4, in5, in6, in7, in8, dataout, reset); input [2:0] addr;input [3:0] in1,in2,in3,in4,in5,in6,in7,in8;input reset;output [3:0] dataout;reg [3:0] dataout;always @(addr or in1 or in2 or in3 or in4 or in5 or in6 or in7 or in8 or reset) beginif(!reset)case(addr)3'b000: dataout = in1;3'b001: dataout = in2;3'b010: dataout = in3;3'b011: dataout = in4;3'b100: dataout = in5;3'b101: dataout = in6;3'b110: dataout = in7;3'b111: dataout = in8;endcaseelsedataout = 0;endendmodule逻辑运算电路module tryfunct(clk, n, result, reset);output[31:0] result;input[3:0] n;input reset, clk;reg[31:0] result;always @(posedge clk)beginif (!reset)result <=0;elsebeginresult <= n*factorial(n)/((n*2)+1);endendfunction [31:0] factorial;input [3:0] operand;reg [3:0] index;beginfactorial = operand ? 1:0;for (index = 2; index <= operand; index = index + 1) factorial = index *factorial;endendfunctionendmodulemodule tryfunct(clk, n, result, reset);output[31:0] result;input[3:0] n;input reset, clk;reg[31:0] result;always @(posedge clk)beginif (!reset)result <=0;elsebeginresult <= n*factorial(n)/((n*2)+1);endendfunction [31:0] factorial;input [3:0] operand;reg [3:0] index;beginfactorial = operand ? 1:0;for (index = 2; index <= operand; index = index + 1) factorial = index *factorial;endendfunctionendmodule高速排序组合逻辑module sort4(ra, rb, rc, rd, a, b, c, d);output[3:0] ra, rb, rc, rd;input[3:0] a, b, c, d;reg[3:0] ra, rb, rc, rd;reg[3:0] va, vb, vc, vd;always @(a or b or c or d)begin{va, vb, vc, vd} = {a, b, c, d};sort2(va, vc);sort2(vb, vd);sort2(va, vb);sort2(vc, vd);sort2(vb, vc);{ra, rb, rc, rd} = {va, vb, vc, vd};endtask sort2;input[3:0]x, y;reg[3:0] tmp;if (x > y)begintmp = x;x = y;y = tmp;endendtaskendmodule检测5位二进制序列10010module seqdet(x, z, clk, rst, state);input x, clk, rst;output z;output[2:0] state;reg[2:0] state;wire z;parameter IDLE = 'd0, A = 'd1, B = 'd2, C = 'd3, D = 'd4, E = 'd5, F = 'd6, G = 'd7; assign z = (state == E && x == 0 )? 1:0;always @(posedge clk)if (!rst)beginstate <= IDLE;endelsecase (state)IDLE:if (x == 1)beginstate <= A;endA:if (x == 0)beginstate <= B;endB:if (x == 0)beginstate <= C;endelsebeginstate <= F;endC:if (x == 1)beginstate <= D;endelsebeginstate <= G;endD:if (x == 0)beginstate <= E;endelsebeginstate <= A;endE:if (x == 0)beginstate <= C;endelsebeginstate = A;endF:if (x == 1)beginstate <= A;endelsebeginstate <= B;endG:if (x == 1)beginstate <= F;enddefault:state = IDLE;endcaseendmodule模拟电路部分1.目前，集成电路最常用的材料是单晶硅。