Problem: 考虑动态RAM每毫秒必须刷新64次，每次刷新操作 需要150ns，一个存储周期需要250ns。问：存储器 总操作时间的百分之多少必须用于刷新。
Analysis:
In 1 ms, the time devoted to refresh is 64 × 150 ns = 9600 ns. The fraction of time devoted to memory refresh is (9.6 × 10–6 s)/10–3 s = 0.0096, which is approximately 1%.
Problem: 假定访问DRAM时分别传送行地址和列地址（存取时间由时刻t1到t2）。由 t2到t3是刷新时间，这段时间内数据输出有效。 (a)假定存取时间是60ns，刷新时间40ns。问：存取周期时间是多少？假定1 位输出，这个DRAM所支持的最大传输率是多少？ (b)使这些芯片构成一个32位宽的存储系统，其产生的数据传输率是多少？
Answer：
a. Memory cycle time = 60 + 40 = 100 ns. The maximum data rate is 1 bit every 100 ns, which is 10 Mbps. b. 320 Mbps = 40 MB/s.
Problem: 如果使用8个容量为1MB的芯片来构成一个8MB存储器，请画出连接图。图 中一定会有地址线，作用是什么？
a. The refresh period from row to row must be no greater than 4000/256 = 15.625 μs. b. An 8-bit counter is needed to count 256 rows (28 = 256). Source: [PROT88].
A. 21 B. 17 C. 19
下列叙述中正确的是
。
A. 主存可由RAM和ROM组成 B. 主存只能由ROM组成 C. 主存只能由RAM组成
半导体静态RAM依据理 存储信息。
用1K×4位的存储芯片组成容量为 64K×８位的存储器共需 128 片， 若将这些芯片分装在几块板上，设每 块板的容量为16K×８位，则该存储 器所需的地址码总位数是 16 ， 2 其中 位用于选板， 4 位 用于选片， 10 位用于存储芯片 的片内地址。
CHAPTER 5 INTERNAL MEMORY
Problem: 半导体存储器的主要性质是什么?
Answer:
They exhibit two stable (or semistable) states, which can be used to represent binary 1 and 0; they are capable of being written into (at least once), to set the state; they are capable of being read to sense the state.
Problem: 说明为何一种类型的RAM被认为是模 拟设备，而另一种类型的RAM被认为 是数字设备？
Answer:
A DRAM cell is essentially an analog device using a capacitor; the capacitor can store any charge value within a range; a threshold value determines whether the charge is interpreted as 1 or 0. A SRAM cell is a digital device, in which binary values are stored using traditional flip-flop logicgate configurations.
Problem: 一个实际的微型计算机的存储器用64K×1的DRAM芯片构成。依据数据资料 知道，DRAM的位元阵列组织成256行，无论如何每行必须每4ms刷新一次。 假设系统严格按此要求周期性地刷新存储器。 (a)连续刷新请求之间的时间周期是什么？ (b)所需的刷新地址计数器是多少位？
Answer：
Problem: 传统的RAM组成成每芯片只有1位，而ROM通常 组织成每芯片多位，请说明原因。
Answer:
The 1-bit-per-chip organization has several advantages. It requires fewer pins on the package (only one data out line); therefore, a higher density of bits can be achieved for a given size package. Also, it is somewhat more reliable because it has only one output driver. These benefits have led to the traditional use of 1-bit-perchip for RAM. In most cases, ROMs are much smaller than RAMs and it is often possible to get an entire ROM on one or two chips if a multiple-bits-per-chip organization is used. This saves on cost and is sufficient reason to adopt that organization.
存储周期是指
。
A. 存储器的写入时间 B. 存储器进行连续写操作允许的最短间隔时间 C. 存储器进行连续读或写操作允许的最短间隔时间
一个16K×32位的存储器，其地址线和数据线 的总和是 。
A. 48 B. 46 C. 36
某一RAM芯片，其容量是512×8位， 除电源和接地端外，该芯片引出线的 最少数目是 。
Problem: 术语“随机存取存储器”使用上有哪两种意 思？
Answer: (1) A memory in which individual words of memory are directly accessed through wired-in addressing logic. (2) Semiconductor main memory in which it is possible both to read data from the memory and to write new data into the memory easily and rapidly.