Integrated System Design Lab.
2
Introduction
?Moore's law
– Performance & density improvement in digital system
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Digital System Performance
?Performance bottleneck
– The cost of arithmetic operation is cheap now
Computation - bound
Communication - bound
“Pentium Pro”
Integrated System Design Lab.
3
Introduction
?Moore's law
Growing gap limits system performance!!
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103101102Fra bibliotek101
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Integrated System Design Lab.
6
Parallel Bus & Serial Link
Core
Parallel Bus Data
I/O
I/O
Clock
Core
? Group data (Bus) ? Source synchronous ? Matched trace
Core
Serial Link
Serial
Data
I/O
I/O
?High-speed, low voltage swing interface
Termination
VTT
( R = Z0 )
VRR
Driver
Channel Z0 Z0
DC block
To CDR
Limiting amp
?Usually, differential ?Small swing - ~ several hundreds mV
10 ~ 20 cycles / Arithmetic operation 70 cycles / DRAM access
“Pentium 4”
20 ~ 30 cycles / Arithmetic operation 500 ~ 600 cycles / DRAM access
Integrated System Design Lab.
Detector
Filter
Oscillator
Di 0 1 1 0 1 0 0 1 0 0 0
CKr
Do
Integrated System Design Lab.
12
Link Performance Metric
?Eye diagram & jitter Tbit
Random bit sequence
“serial link”or “seria-llink-like parallel b
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Serial Link Architecture
Transmitter PCS Serializer
Transmitter + Receiver = Transceiver
Framer
Channel
PLL Receiver
Latency
Parallel Bus Low Short
Speed
~ 200Mbps / pin
Manufacturing Cost
High
Serial Link High
Long ~ 10Gbps / pin
or more Low
World is moving toward us”!!
Integrated System Design Lab.
5
Computing System
?High-speed I/O is needed everywhere
Display Long distance Switch
Graphic Disk LAN
CPU
North Bridge
South Bridge
Memory Local I/O
SAN
Integrated System Design Lab.
Detector
Filter
Oscillator
CKo ( fout )
?M
?Frequency multiplication: ?Jitter filter ?Zero-delay buffer
fout = M·fin
Integrated System Design Lab.
10
Link Component
Deserializer PCS
Deframer
Integrated System Design Lab.
Clock recovery
9
Link Component
?Phase-locked Loop (PLL)
CKi ( fin )
Phase error Loop- Vctr Voltage-Controlled
High-Speed Serial Link
Deog-Kyoon Jeong
Seoul National University
Outline
? Introduction ?High-speed I/O overview ?Hot design issues ?Design examples ? Summary
Integrated System Design Lab.
11
Link Component
?Clock & data recovery (CDR) circuits
Decision circuit Do
Di
NRZ Phaseerror Loop- Vctr Voltage-Controlled CKr
Core
? Single trace ? Plesiochronous ? Clock embedded in data ? Clock & data recovery
Integrated System Design Lab.
7
Parallel vs. Serial
Hardware Co mplexity
Eye diagram Jitter histogram
Integrated System Design Lab.
Tbit Ideal
Timing uncertainty : Jitter Realistic
13
Link Performance Metric