湖南大学HUNAN UNIVERSITY硬件基础实验2实验报告一、实验预习1.书中的图形实现微程序控制器，中间的映射逻辑究竟是怎么实现的？答：但出现分支时，预设端信号由IR决定。

IR为1时信号有效，输出为1.通过IR的值映射为下址的低三位，从而产生下址。

2.书中设计用到了强写强读，为什么要设计这个功能？答：满足用户因为没有初始化mif文件时输入数据的需要。

二、实验目的微程序控制器实验的主要任务：生成CPU里的控制信号，并使程序按正确的顺序执行。

核心部分是ROM，存放机器指令的微程序。

1、掌握微程序控制器的组成、工作原理；2、掌握微程序控制器的基本概念和术语：微命令、微操作、微指令、微程序等；3、掌握微指令、微程序的设计及调试方法；4、通过单步运行若干条微指令，深入理解微程序控制器的工作原理；二、实验电路图1附：电路图过大，请放大观察详情三、实验原理将机器指令的操作（从取指到执行）分解为若干个更基本的微操作序列，并将有关的控制信息（微命令）以微码的形式编成微指令输入到控制存储器中。

这样，每条机器指令将与一段微程序对应，取出微指令就产生微命令，以实现机器指令要求的信息传送与加工。

四、实验步骤及概述1)设计状态机部分a、编写VHDL代码如下LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY zhuangtaiji ISPORT (reset : IN STD_LOGIC := '0';clock : IN STD_LOGIC;qd : IN STD_LOGIC := '0';dp : IN STD_LOGIC := '0';tj : IN STD_LOGIC := '0';t1 : OUT STD_LOGIC;t2 : OUT STD_LOGIC;t3 : OUT STD_LOGIC;t4 : OUT STD_LOGIC);END zhuangtaiji;ARCHITECTURE BEHAVIOR OF zhuangtaiji IS TYPE type_fstate IS(idle,st1,s_st2,st4,st2,st3,s_st4,s_st3);SIGNAL fstate : type_fstate;SIGNAL reg_fstate : type_fstate;BEGINPROCESS (clock,reset,reg_fstate)BEGINIF (reset='1') THENfstate <= idle;ELSIF (clock='1' AND clock'event) THEN fstate <= reg_fstate;END IF;END PROCESS;PROCESS (fstate,qd,dp,tj)BEGINt1 <= '0';t2 <= '0';t3 <= '0';t4 <= '0';CASE fstate ISWHEN idle =>IF (NOT((qd = '1'))) THENreg_fstate <= st1;ELSEreg_fstate <= idle;END IF;t1 <= '0';t2 <= '0';t4 <= '0';WHEN st1 =>IF (((tj = '1') AND NOT((dp = '1')))) THENreg_fstate <= st1;ELSIF (((dp = '1') AND NOT((tj = '1')))) THENreg_fstate <= s_st2;ELSEreg_fstate <= st2;END IF;t1 <= '1';t2 <= '0';t3 <= '0';t4 <= '0';WHEN s_st2 =>IF ((tj = '1')) THENreg_fstate <= s_st2;ELSEreg_fstate <= s_st3;END IF;t2 <= '1';t3 <= '0';t4 <= '0';WHEN st4 =>IF (((tj = '1') AND NOT((dp = '1')))) THENreg_fstate <= st4;ELSIF (((dp = '1') AND NOT((tj = '1')))) THENreg_fstate <= idle;ELSEreg_fstate <= st1;END IF;t1 <= '0';t2 <= '0';t3 <= '0';t4 <= '1';WHEN st2 =>IF (((tj = '1') AND NOT((dp = '1')))) THENreg_fstate <= st2;ELSIF (((dp = '1') AND NOT((tj = '1')))) THENreg_fstate <= s_st3;ELSEreg_fstate <= st3;END IF;t1 <= '0';t2 <= '1';t3 <= '0';t4 <= '0';WHEN st3 =>IF (((tj = '1') AND NOT((dp = '1')))) THENreg_fstate <= st3;ELSIF (((dp = '1') AND NOT((tj = '1')))) THENreg_fstate <= s_st4;ELSEreg_fstate <= st4;END IF;t1 <= '0';t2 <= '0';t3 <= '1';t4 <= '0';WHEN s_st4 =>IF ((tj = '1')) THENreg_fstate <= s_st4; ELSEreg_fstate <= idle; END IF;t1 <= '0';t2 <= '0';t3 <= '0';t4 <= '1';WHEN s_st3 =>IF ((tj = '1')) THENreg_fstate <= s_st3; ELSEreg_fstate <= s_st4; END IF;t1 <= '0';t2 <= '0';t3 <= '1';t4 <= '0';WHEN OTHERS =>t1 <= 'X';t2 <= 'X';t3 <= 'X';t4 <= 'X';report "Reach undefined state";END CASE;END PROCESS;END BEHAVIOR;b、新建block file选定zhaungtaiji得到电路图2)设计rom部分a、编写VHDL代码如下LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY rom ISPORT(address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);q : OUT STD_LOGIC_VECTOR (27 DOWNTO 0));END rom;ARCHITECTURE SYN OF rom ISSIGNAL sub_wire0 : STD_LOGIC_VECTOR (27 DOWNTO 0);BEGINsub_wire0<="1011000000100000010100000001" WHEN address= "00000" ELSE"1110100100100000010101100010" WHEN address= "00001" ELSE"1001000100100000010100101000" WHEN address= "00010" ELSE"1110100100100000010100010101" WHEN address= "01001" ELSE"1001101100100000010100010110" WHEN address= "10101" ELSE"1001001100100000011100000001" WHEN address= "10110" ELSE"01010" ELSE "1001101100100000010100011000" WHEN address= "10111" ELSE "1001010100100000010000000001" WHEN address= "11000" ELSE "1110100100100000010100011001" WHEN address= "01011" ELSE "1001101100100000010100011010" WHEN address= "11001" ELSE "1001001100100000010100000001" WHEN address= "11010" ELSE "1001000101100000010000011011" WHEN address= "01100" ELSE "1001000100110000001100000001" WHEN address= "11011" ELSE "1110100100100000010100011100" WHEN address= "01101" ELSE "1011001100100000010100000001" WHEN address= "11100" ELSE "1110100100100000010100000011" WHEN address= "01110" ELSE"00011" ELSE "1001001100100000010110000101" WHEN address= "00100" ELSE "1001000101100000010000000110" WHEN address= "00101" ELSE "1001000100101001101100000001" WHEN address= "00110" ELSE "1110100100100000010100011101" WHEN address= "01111" ELSE "1001101100100000010100011110" WHEN address= "11101" ELSE "1001001100100000010110011111" WHEN address= "11110" ELSE "1001000101100000010000000111" WHEN address= "11111" ELSE "1001000100100001111100000001" WHEN address= "00111" ELSE "1011000000100000010100010011" WHEN address= "01000" ELSE "1110100100100000010100010100" WHEN address= "10011" ELSE"10100" ELSE"1011000000100000010100010001" WHEN address="10000" ELSE"1110100100100000010100010010" WHEN address="10001" ELSE"1001010000100000010100010001" ;q <= sub_wire0(27 DOWNTO 0);END SYN;b、新建block file选定rom得到电路图3)、整合电路图整合电路图如图1所示。