l 描述
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • module FSM(clk,clr,out,start,step2,step3); input clk,clr,start,step2,step3; output[2:0] out; reg[2:0] out; reg[1:0] state,next_state; parameter state0=2'b00,state1=2'b01, state2=2'b11,state3=2'b10; always @(posedge clk or posedge clr) begin if (clr) state <= state0; else state <= next_state; end always @(state or start or step2 or step3) begin case (state) state0: begin if (start) next_state <=state1; else next_state <=state0; end state1: begin next_state <= state2; end state2: begin if (step2) next_state <=state3; else next_state <=state0; end state3: begin if (step3) next_state <=state0; else next_state <=state3; end default: next_state <=state0; endcase end always @(state) begin case(state) state0: out=3'b001; state1: out=3'b010; state2: out=3'b100; state3: out=3'b111; default:out=3'b001; endcase end endmodule
D锁存器
• module D_latch(Q,D,E); • output Q; • input D,E; • reg Q; • always @ (E or D) • if (E) Q<=D; //same as: if (E==1) • endmodule
D触发器
• module D_FF(Q,D,CP); • output Q; • input D,CP; • reg Q; • always @ (posedge CP) • Q<=D; • endmodule
always结构的要点
• 在一个always块中只能用阻塞或非阻塞一 种赋值方式。 • 不要在一个以上的always块中对同一个变 量赋值。
复杂D触发器
• • • • • • • • • • • • • • • • • • • module D_FF(Q,QN,D,CP,Sd,Rd); output Q,QN; input D,CP,Sd,Rd; reg Q,QN; always @ (posedge CP or negedge Sd or negedge Rd) if (~Sd ||~Rd) // 置1与置0 低电平有效 if(~Sd) begin Q<=1'b1; QN<=1'b0; end else begin Q<=1'b0; QN<=1'b1; end else begin Q<=D; Q<=~D; end endmodule //异步置1与置0
计数器
• • • • • • • • • • • • • • • module counter74161 (CEP,CET,PE,D,CP,CR,Q,TC); input CEP,CET,PE,CP,CR; input[3:0] D; output TC; output [3:0] Q; reg[3:0] Q; wire CE; assign CE=CEP&CET; assign TC=CET&(Q==4'b1111); always @(posedge CP or negedge CR) if(~CR) Q<=4'b0000; else if (~PE) Q<=D; else if (~CE) Q<=Q; else Q<=Q+1'b1; endmodule
时序逻辑电路verilog_hdl建模
always initial
always结构
always @ (敏感事件） begin //逻辑描述 end
敏感事件
• 电平敏感 • 边沿敏感 posedge 用变量名表达 ( verilog_hdl关键字 ) negedge
阻塞与非阻塞赋值
• 阻塞赋值 ＝ • 非阻塞赋值 <= begin begin B=A; B<=A; C=B+1; C<=B+1; end end
移位寄存器
• • • • • • • • • • • • • • • • • module shift74194(S1,S0,D,Dsl,Dsr,Q,CP,CR); ////p303 input S1,S0; input Dsl,Dsr; input CP,CR; input[3:0] D; output[3:0] Q; reg[3:0] Q; always @(posedge CP or negedge CR) if( ~CR) Q<=4'b0000; else case ({S1,S0}) 2'b00 :Q<=Q; 2'b01 : Q<={Q[2:0],Dsr}; 2'b10 : Q<={Dsl,Q[3:1]}; 2'b11 : Q<=D; endcase endmodule