OUTV SSC_SEL SSC_SEL INSSC_SEL 0SSC_SEL 1GNDVDD OE OUT FSCDCS503-Q1ZHCS946B –MARCH 2012–REVISED JUNE 2012带有可选展频时钟(SSC)的时钟缓冲器/时钟倍乘器查询样品:CDCS503-Q1特性•符合汽车应用要求•单一3.3V 器件电源•具有下列结果的AEC-Q100测试指南：•宽温度范围-40°C 至105°C–器件温度2级•节省空间的8引脚薄型小外形尺寸(TSSOP)封装–-40°C 至105°C 环境温度范围应用范围–器件人体模型(HBM)静电放电(ESD)分类等级•要求通过SSC 和/或者时钟倍乘来减少电磁干扰H2(EMI)的车载应用–器件充电器件模型(CDM)ESD 分类等级C3B •带有可选展频时钟(SSC)的易于使用的时钟生成器产品的一部分•带有可选输出频率和可选SSC 的时钟倍乘器•通过两个外部引脚可控制SSC–±0%，±0.5%，±1%，±2%中心展频•可使用一个外部控制引脚来选择x1或者x4的频率倍乘•通过控制引脚进行输出禁用图1.方框图Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.CDCS503-Q1ZHCS946B–MARCH2012–REVISED 说明CDCS503-Q1是一款带有可选频率倍乘的可展频、LVCMOS输入时钟缓冲器。

它与CDCS502共用主要的功能性，但是它使用一个LVCMOS输入级而不是CDCS502所使用的晶振输入级，并且CDCS503-Q1有一个输出使能引脚。

此器件在输入上接受一个3.3V LVCMOS信号。

这个输入信号由一个锁相环路(PLL)处理，此环路的输出频率或者与输入频率相等或者被乘以因子4。

PLL还可通过三角调制将时钟信号以输出时钟频率为中心扩展±0%，±0.5%，±1%或者±2%。

这样，此器件可生成介于8MHz和108MHz之间带有或者不带有SSC的输出频率。

一个独立的控制引脚可被用于启用或者禁用输出。

CDCS503-Q1运行在一个3.3V环境中。

器件额定运行温度介于-40°C至105°C之间，并采用8引脚TSSOP封装。

表1.功能表OE FS SSC_SEL0SSC_SEL1SSC数量f OUT/f IN f in=27MHz时的f OUT 0x x x x x三态1000±0.00%127MHz1001±0.50%127MHz1010±1.00%127MHz1011±2.00%127MHz1100±0.00%4108MHz1101±0.50%4108MHz1110±1.00%4108MHz1111±2.00%4108MHzIN SSC_SEL0 SSC_SEL1GND VDD OE OUTFS CDCS503-Q1 ZHCS946B–MARCH2012–REVISED JUNE2012这些装置包含有限的内置ESD保护。

存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止MOS门极遭受静电损伤。

DEVICE INFORMATIONPACKAGEPIN FUNCTIONSSIGNAL PIN TYPE DESCRIPTIONIN1I LVCMOS clock inputOUT6O LVCMOS clock outputSSC_SEL0,12,3I Spread selection pins,internal pullupOE7I Output enable,internal pullupFS5I Frequency multiplication selection,internal pullupVDD8Power 3.3-V power supplyGND4Ground GroundORDERING INFORMATIONT A PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to105°C TSSOP2000CDCS503TPWRQ1CS503QPACKAGE THERMAL RESISTANCE FOR TSSOP(PW)PACKAGEover operating free-air temperature range(unless otherwise noted)(1)THERMAL AIRFLOW(CFM)PW8-PIN TSSOP UNIT0150250500 High K149142138132RθJA°C/W Low K230185170150High K65RθJC°C/W Low K69(1)The package thermal impedance is calculated in accordance with JESD51and JEDEC2S2P(high-k board).THERMAL INFORMATIONCDCS503TPWRQ1THERMAL METRIC(1)UNITPW(8PINS)θJA Junction-to-ambient thermal resistance179.9θJCtop Junction-to-case(top)thermal resistance64.9θJB Junction-to-board thermal resistance108.7°C/WψJT Junction-to-top characterization parameter9ψJB Junction-to-board characterization parameter107θJCbot Junction-to-case(bottom)thermal resistance n/a(1)有关传统和全新热度量的更多信息，请参阅IC封装热度量应用报告（文献号：SPRA953）。

CDCS503-Q1ZHCS946B–MARCH2012–REVISED ABSOLUTE MAXIMUM RATINGS(1)over operating free-air temperature range(unless otherwise noted)VALUE UNITV DD Supply voltage range–0.5to4.6VV IN Input voltage range–0.5to4.6VV out Output voltage range–0.5to4.6VI IN Input current(V I<0,V I>V DD)20mAI out Continuous output current50mAT ST Storage temperature range–65to150°CT J Maximum junction temperature125°C ESD Rating Human-body model(HBM)AEC-Q100classification level H2 1.5kV Charged-device model(CDM)AEC-Q100classification level C3B750V (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.CDCS503-Q1 ZHCS946B–MARCH2012–REVISED JUNE2012RECOMMENDED OPERATING CONDITIONSMIN NOM MAX UNITV DD Supply voltage3 3.6VFS=0832f IN Input frequency MHzFS=1827V IL Low-level input voltage LVCMOS0.3V DD VV IH High-level input voltage LVCMOS0.7V DD VV I Input voltage threshold LVCMOS0.5V DD VC L Output load test LVCMOS15pFI OH/I OL Output current±12mAT A Operating free-air temperature–40105°C DEVICE CHARACTERISTICSover recommended operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITf out=20MHz;FS=0,no SSC19I DD Device supply current mAf out=70MHz;FS=1,SSC=2%22FS=0832f OUT Output frequency MHzFS=132108I IH LVCMOS input current V I=V DD;V DD=3.6V10μAI IL LVCMOS input current V I=0V;V DD=3.6V–10μAI OH=-0.1mA 2.9V OH LVCMOS high-level output voltage I OH=-8mA 2.4VI OH=-12mA 2.2I OL=0.1mA0.1V OL LVCMOS low-level output voltage I OL=8mA0.5VI OL=12mA0.8I OZ High-impedance-state output current OE=Low–22μAt JIT(C-C)Cycle to cycle jitter(1)f out=108MHz;FS=1,110psSSC=1%,10000Cyclest r/t f Rise and fall time(1)20%–80%0.75nsO dc Output duty cycle(2)45%55%f MOD Modulation frequency30kHz(1)Measured with Test Load,see Figure3.(2)Not production tested.10 pF051015202530354005101520253035f - Input Frequency - MHzi I - I n p u t C u r r e n t - m AD D CDCS503-Q1ZHCS946B –MARCH 2012–REVISED JUNE 2012Figure 2.I DD vs Input Frequency,V CC =3.3V,SSC =2%,Output Loaded With Test LoadAPPLICATION INFORMATIONSSC MODULATIONThe exact implementation of the SSC modulation plays a vital role for the EMI reduction.The CDCS503-Q1device uses a triangular modulation scheme implemented in a way that the modulation frequency depends on the VCO frequency of the internal PLL and the spread amount is independent from the VCO frequency.The modulation frequency can be calculated by using one of the below formulas chosen by frequency multiplication mode.FS =0:f mod =f IN /708FS =1:f mod =f IN /620PARAMETER MEASUREMENT INFORMATIONFigure 3.Test LoadCDCS503-Q1Impedance ~ 32W ~ 18WCDCS503-Q1 ZHCS946B–MARCH2012–REVISED JUNE2012 PARAMETER MEASUREMENT INFORMATION(continued)Figure4.Load for50-ΩBoard EnvironmentCDCS503-Q1ZHCS946B–MARCH2012–REVISED REVISION HISTORYChanges from Revision A(June2012)to Revision B Page •在FAD中将符合AEC Q100标准改为了AEC Q100测试指南 (1)PACKAGING INFORMATION(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF CDCS503-Q1 :•Catalog: CDCS503Addendum-Page 1NOTE: Qualified Version Definitions:•Catalog - TI's standard catalog productAddendum-Page 2TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CDCS503TPWRQ1TSSOPPW82000330.012.47.03.61.68.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm)CDCS503TPWRQ1TSSOP PW82000367.0367.035.0PACKAGE OUTLINETSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGENOTES:1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153, variation AA.EXAMPLE BOARD LAYOUT PW0008ATSSOP - 1.2 mm max heightSMALL OUTLINE PACKAGE ArrayNOTES: (continued)6. Publication IPC-7351 may have alternate designs.7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.EXAMPLE STENCIL DESIGN PW0008ATSSOP - 1.2 mm max heightSMALL OUTLINE PACKAGE ArrayNOTES: (continued)8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.9. Board assembly site may have different recommendations for stencil design.重要声明德州仪器(TI)及其下属子公司有权根据JESD46最新标准,对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权根据JESD48最新标准中止提供任何产品和服务。