18

基于DaVinCi平台的软件开发流程
19

基于DaVinCi平台的软件开发流程
20
xDAIS和xDM算法接口标准
21

Video Acceleration Strategies
Time to Market
(C64+, StarCore, CEVA, Trimedia)
} } }
Codec
HDVICP
Fixed Kernel Functions Header Processing Codec Software
Multi-format support Multi-channel support for sub-HD video High-BW DMA access to MB-level processing buffers for codec expansion
} } }
}
eXpressDSP Configuration Kit TMS320DM644x SoC Analyzer MontaVista’s Linux
} }
Digital Video Evaluation Module TI third party development boards
10

14

目标应用
Trans Code
MPEG2 HD MPEG2 HD MPEG2 SD MPEG2 SD MPEG2 HD MPEG2 HD H.264 HD VC-1 HD H.264 SD VC-1 SD H.264 SD VC-1 SD
HD Decode
MPEG2 HD H.264 HD VC-1 HD
•Multiple DSP with programmable acceleration
m for •DSP+VICP per •DSP+HDVICP her ig H
•Higher Frequency DSPs with Prog. acceleration
•DSP
ly e, ful c rman perfo er High
Trans Rate
H.264 HD VC-1 HD H.264 HD VC-1 HD
SD Encode/Decode
MPEG2 SD H.264 SD VC-1 SD
15

VISA 的基本概念
16

使用 VISA 的优点
17

基于DaVinCi平台的软件开发流程
EDMA SS
PLL PLL CTRL
PLL PLL CTRL
ICEPick
PSC
JTAG
27 MHz
24 MHz
13

DM6467 vs. DM6446
v Addition to DM6447
New New New New New
v PCI (32bit and 33Mhz) v UHPI (16/32 bit mode) v Video Port v Video Data Conversion Engine (VDCE) v Transport Stream Interfaces (TSIF) v Clock Reference Generator (CRGEN) v 2 HDVICP – not covered here v 2 McASP v 3 UART
Algorithm-specific hardware accelerators Multi-format All fixed kernel functions accelerated All programmable functions in DSP High-BW DMA data exchange Full HD Decoding (all profile) 720p single-silicon encoding (baseline profile) Multi-silicon scalability Minimum processing delay variation Full API support Command-driven, no assembler needed Configurable via register control MB-level codec control
DVSDK工具链
}
eXpressDSP Configuration Kit } TI’s video, imaging, speech and audio codecs } Custom codecs that comply with TI’s eXpressDSP™ Digital } Media (xDM) algorithm standard } TI’s codec engine framework } DSP/BIOS™ real-time kernel } TI’s DSP/BIOS Link inter-processor communication } technology TMS320DM644x SoC Analyzer } system interaction } load distribution } bottlenecks in data throughput } other types of behavior
}
11

DVSDK工具链
DVEVM允许开发者为ARM编写即将投入 生产的应用程序代码和使用DaVinci API访问DSP内核，从而立即开始针对 DM6443和DM6446器件的应用开发。
12

DM6467 Block Diagram
PCI-32 (33MHz)
DSP
General Processor (Intel/ARM)
GP/DSP With Coprocessors
Energy Efficiency
Flexibility
Programmable Accelerators Reconfigurable Accelerators
(Stretch)
Hard-wired ASIC

e mabl ogram pr
23
HDVICP Overview
}
Architecture
} } } } }
Codec DSP
Fixed Kernel Functions Header Processing Codec Software Coding Parameter Controls
OR
ARM SS
ARM INTC ARM9 ICECrusher
DSP SS
C64x+ (594 MHz) L1 I-Cache L1 D-Cache 32K 32K L2 Cache 128K
UHPI-32
OR
SCR 150 MHz
ARM926-EJS (297 MHz) I-Cache D-Cache 16K 8K TCM RAM Boot ROM 32K 8K
}
Performance
} } } }
Codec
HDVICP
Fixed Kernel Functions Header Processing
}
Programming
} } } }
We Are Here
DSP
Codec Software Coding Parameter Controls
}
Scalability
HDVICP0 SS ARM968-ES (150/300 MHz) TCM RAM ME IPE MC LF CALC ECD HDVICP1 SS ARM968-ES (150/300 MHz) TCM RAM MC LF CALC ECD
GPIO McASP 1-channel McASP 4-channel I2C SPI PWM x2 Timer64 x3 UART x3 DDR2 PHY / DLL / IOs 300 MHz TSIF
Hale Waihona Puke v ARM (32KB RAM, 8KB ROM, 16KB I-Cache, and 8 KB D-Cache) vGEM (64KB L1P ROM, 32KB L2D, and 128KB L2) v SCR (297 Mhz VBUSM, 148.5 MHz VBUSP and CFG bus) v DDR2 (297 MHz) v 1Gbit Ethernet Mac v EDMA (4 TC)
(MPEG-2 Decoders)
22
System Cost Efficiency

Summary of TI Video Processing Past
ce, an
Today
her hig
icie eff
ncy
Future
•DSP+IVA-HD
•Improved DSP Core
DSP
Coding Parameter Controls
24

HDVICP Capability
(based(full 1080i) Decoding on DM6467 Implementation) HDTV
MPEG2 (MP) H.264 (BP) VC1 (AP), WMV9 720P@30 fps HD Encoding MPEG2 (MP) H.264 (BP) VC1 (AP), WMV H.263, MPEG-4 (SP/ASP) SDTV Simultaneous Encode/Decode MPEG2 (MP) H.264 (MP) VC1 (AP), WMV H.263, MPEG4 (SP/ASP) Transcoder MPEG2(MP@HL) à H.264 HP Level4, MPEG2(MP@HL) à H.264 MP Level3, MPEG2(MP@ML) ßà H.264 MP Level3, MPEG2(MP@ML) ß H.264 HP Level4,