“非”门library ieee;use ieee.std_logic_1164.all; entity not1 isport(a:in std_logic;b:out std_logic); end entity not1; architecture behav of not1 is beginb<=not a;end architecture behav;“与”门library ieee;use ieee.std_logic_1164.all; entity and2 isport(a,b:in std_logic;c:out std_logic); end entity and2; architecture behav of and2 is beginc<=a and b;end architecture behav;“与非”门library ieee;use ieee.std_logic_1164.all; entity nand2 isport(a,b:in std_logic;c:out std_logic); end entity nand2; architecture behav of nand2 is beginc<=not(a and b);end architecture behav; “或非”门library ieee;use ieee.std_logic_1164.all;entity nor2 isport(a,b:in std_logic;c:out std_logic);end entity nor2;architecture one of nor2 isbeginc<=not(a or b);end architecture one;“异或非”门library ieee;use ieee.std_logic_1164.all;entity xor2 isport(a,b:in std_logic;c:out std_logic);end entity xor2;architecture one of xor2 isBeginc<=not( ( (not a)and b)or(aand(not b) ) );end architecture one;D触发器library ieee;use ieee.std_logic_1164.all;entity dffa isport(D,clk,clr:in std_logic;Q:out std_logic);end entity dffa;architecture behave of dffa isbeginprocess(clk,D,clr)beginif clr='1' then Q<='0';Elsif clk'event and clk='1'then Q<=D;end if;end process;end architecture behave;T触发器library ieee;use ieee.std_logic_1164.all;entity tffa isport(T,clk,clr: in std_logic;Q: buffer std_logic);end entity tffa;architecture behave of tffa isbeginprocess(clk,T,clr)beginif clk'event and clk='1'thenif clr='1' then Q<='0';Elsif t='1'then Q<=not Q;else Q<=Q;End if;end if;end process;end architecture behave;JK触发器library ieee;use ieee.std_logic_1164.all;entity jk isport(J,K,clk, in std_logic;Q: buffer std_logic);end entity tffa;architecture behave of jk isbeginprocess(clk,J,K)beginif clk'event and clk='1'thenQ<=( (J and(not Q) )or( (notK)and Q) );end if;end process;end architecture behave;移位寄存器library ieee;use ieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entity reg isport(clk,din, dir: in std_logic;op: out std_logic);end entity reg;architecture a of reg issignal q:std_logic_vector(7 downto 0);beginprocess(clk)beginif clk'event and clk='1'thenif dir='0' then q(0)<=din;for i in 1 to 7 loopq(i)<=q(i-1);end loop;else q(7)<=din;for i in 1 to 7 loopq(i-1)<=q(i);end loop;end if;end if;end process;op<=q(7)when dir='0'elseq(0);end architecture a; 分频电路library ieee;use ieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entity divf isport(clk: in std_logic;q: out std_logic);end entity divf;architecture a of divf issignal rst:std_logic;signal qn:std_logic_vector(2downto 0);beginprocess(clk,rst)beginif rst='1'then qn<="000";elsifclk'event and clk='1'thenqn<=qn+1;end if;end process;rst<='1'when qn=6 else'0';q<= qn(2);end architecture a;74LS160计数器library ieee;use ieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entity ls74160 isport(clk,rst,ena,pe:instd_logic;d:in std_logic_vector(3 downto0);count:out std_logic_vector(3downto 0);co:out std_logic);end;architecture behave of ls74160issignal temp:std_logic_vector(3 downto 0);beginprocess(clk,rst,ena,pe)beginif (rst='1')thentemp<="0000";elsif(clk'eventandclk='1')thenif ena='1'thenif pe='1'then temp<=d;elsif temp="1001"thentemp<="0000";co<='1';else temp<=temp+1;co<='0';end if;end if;end if;end process;count<=temp;end behave;10进制计数器library ieee;use ieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entity count10 isport(clk,rst,ena:in std_logi c; count:out std_logic_vector(3 downto 0);co:out std_logic);end count10;architecture behave of count10 issignal temp:std_logic_vector (3 downto 0);beginprocess(clk,rst,ena)beginif (rst='1')thentemp<="0000";elsif(clk'event and clk='1')then if ena='1'thenif(temp="1001")thentemp<="0000";co<='1';else temp<=temp+1;co<='0';end if;end if;end if;end process;count<=temp;end behave;输出逻辑宏单元(OLMC)：输出引脚为12～19共8个。

输出逻辑宏单元包括或门、异或门、D触发器、4个4选1多路选择器、输出缓冲器等。

BCD—7段译码library ieee;use ieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entity decord7 isport(a:in std_logic_vector(3downto 0);q:out std_logic_vector(6downto 0);en:out std_logic);end decord7;architecture behave of decord7isbeginprocess(a)begincase a(3 downto 0) iswhen"0000"=>q<="0111111";when"0001"=>q<="0000110";when"0010"=>q<="1011011";when"0011"=>q<="1001111";when"0100"=>q<="1100110";when"0101"=>q<="1101101";when"0110"=>q<="1111101";when"0111"=>q<="0000111";when"1000"=>q<="1111111";when"1001"=>q<="1101111";when others=>q<="0000000";end case;end process;en<='0';end behave;输入缓冲器：输入端为引脚2～9，共有8个输入。