1. Shown below are buffer-chain designs.(1) Calculate the minimum delay of a chain of inverters for the overalleffective fan-out of 64/1.Solution ：由题可知：64=F 根据经验6.3=opt f 为最合适的值，所以6.364===N N F f ，所以24.3=N ，但是级数必须为整数所以取3=N ，又因为1=γ，所以：15)641(3,464303=+⨯===p p t t f ，所以时最合适4=f 。

(2) Using HSPICE and TSMC 0.18 um CMOS technology model with1.8 V power supply, design a circuit simulation scheme to verify themwith their correspondent parameters of N, f, and t p .Solution:根据（1）中计算知道三级最合适，所以验证如下：A ）、一级无负载测本征延时代码如下：.title buffer-chain 1.lib 'C:\synopsys\Hspice_D-2010.03-SP1\tsmc018\mm018.l' TT * set0.18um library.opt scale=0.1u * set lambda.options post=2 list.temp 27.global vddVdd vdd gnd 1.8vin vin 0 0.9 pulse 0 1.8 25n 5p 5p 49.99n 100n $频率为10MhzCl vout gnd 0f $Cg1=2.46fF，负载为CL=157.44fF.subckt inv in out wn=3.5 wp=10 t=7.5mn out in gnd gnd NCH l=2 w=wn ad='wn*t' pd='wn+2*t' as='wn*t' ps='wn+2*t'mp out in vdd vdd PCH l=2 w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'.endsX1 vin vout inv wn=3.5 wp=10 t=7.5.op.tran 5p 5n.meas tran voutmax max v(vout) from=5p to=5n.meas tran voutmin min v(vout) from=5p to=5n$一级.meas tran tphl1+trig v(vin)+val=0.9+rise=1+targ v(vout)+val='0.5*(voutmax-voutmin)+voutmin'+fall=1.meas tran tplh1+trig v(vin)+val=0.9+fall=1+targ v(vout)+val='0.5*(voutmax-voutmin)+voutmin'+rise=1.end1）一级无负载测得本征延时约为17ps；2）带上64倍Cg1大小的负载测得延时为750.35ps，是本征延时的44倍B）、三级带负载测延时代码如下：.title buffer-chain 3.lib 'C:\synopsys\Hspice_D-2010.03-SP1\tsmc018\mm018.l' TT * set 0.18um library.opt scale=0.1u * set lambda.options post=2 list.temp 27.global vdd.param fan=4Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0 1.8 25n 5p 5p 49.99n 100nCl vout gnd 0f $Cg1=2.46fF，负载为CL=157.44fF.subckt inv in out wn=3.5 wp=10 t=7.5mn out in gnd gnd NCH l=2 w=wn ad='wn*t' pd='wn+2*t' as='wn*t' ps='wn+2*t'mp out in vdd vdd PCH l=2 w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'.endsX1 vin 2 inv wn=3.5 wp=10 t=7.5X2 2 3 inv wn='fan*3.5' wp='fan*10' t=5X3 3 vout inv wn='fan*fan*3.5' wp='fan*fan*10' t=5.op.tran 50p 500n.meas tran voutmax max v(vout) from=50p to=500n.meas tran voutmin min v(vout) from=50p to=500n$三级.meas tran tphl3+trig v(vin)+val=0.9+rise=1+targ v(vout)+val='0.5*(voutmax-voutmin)+voutmin'+fall=1.meas tran tplh3+trig v(vin)+val=0.9+fall=1+targ v(vout)+val='0.5*(voutmax-voutmin)+voutmin'+rise=11）带上64倍Cg1大小的负载测得延时为174.6ps ，是本征延时的10.27倍总结如下：经过调整参数近似时每一级的1=γ，所以经过手工计算得到一级带负载和三级带负载的延时比值为：2344.065151300==p p t t tp tp ，而仿真得到的结果为2327.035.7506.174=，所以符合手工计算的比值，同理其他级的延时代码也是如上的写法，经过仿真得到三级延时最小。

.end2. Consider the logic network below, which may represent the criticalpath of a more complex logic block. The output of the network isloaded with a capacitance which is 5 times larger than the inputcapacitance of the first gate, which is a minimum-sized inverter. Theeffective fanout of the path hence equals F = C L /Cg1 = 5.Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 Vpower supply, design a circuit simulation scheme to verify theOPTIMAZATION parameters of g , f , and s for each of the inverter andgates.Solution: 由题得到路径逻辑努力925135351=⨯⨯⨯=G ，由于没有分支B =1，所以9125==GFB H ，所以使延时最小的逻辑努力为93.191254===N H h ，得到如下的扇出系数：93.1,16.1,16.1,93.14321====f f f f ，利用书上公式6.18计算得到尺寸系数6.2/,34.1/,16.1/,14132143121321121=======g g f f f S g g f f S g g f S S 。

电路仿真代码如下：.title INV 2NAND 2NOR.lib 'C:\synopsys\Hspice_D-2010.03-SP1\tsmc018\mm018.l' TT * set0.18um library.options post=2 list.temp 27.global vddVdd vdd gnd 1.8vin vin 0 0.9 pulse 0.0 1.8 150p 5p 5p 290p 600pC1 vout gnd 12.3f $Cg1=2.46fF，所以负载为12.3fF.subckt inv1 in out wn=0.35u wp=1u t=0.75umn out in gnd gnd NCH l=0.2u w=wn ad='wn*t' pd='wn+2*t' as='wn*t' ps='wn+2*t'mp out in vdd vdd PCH l=0.2u w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'.ends.subckt nand3 NAND-A1 NAND-D1 NAND-B1 NAND-C1 wn='0.35u*1.16' wp='1u*1.16't=0.5u $优化尺寸系数S2*.subckt nand3 NAND-A1 NAND-D1 NAND-B1 NAND-C1 wn=0.35u wp=1u t=0.5u $未优化尺寸系数S2mn3 NAND-S2 NAND-C1 gnd gnd NCH l=0.2u w=wn ad='wn*t' pd='wn+2*t' as='wn*t' ps='wn+2*t'mn2 NAND-S1 NAND-B1 NAND-S2 gnd NCH l=0.2u w=wn ad='wn*t' pd='wn+2*t' as='wn*t' ps='wn+2*t'mn1 NAND-D1 NAND-A1 NAND-S1 gnd NCH l=0.2u w=wn ad='wn*t'pd='wn+2*t' as='wn*t' ps='wn+2*t'mp1 NAND-D1 NAND-A1 vdd vdd PCH l=0.2u w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'mp2 NAND-D1 NAND-B1 vdd vdd PCH l=0.2u w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'mp3 NAND-D1 NAND-C1 vdd vdd PCH l=0.2u w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'.ends.subckt nor2 NOR-A1 NOR-D1 NOR-B1 wn='0.35u*1.34' wp='1u*1.34' t=0.5u $优化尺寸系数S3*.subckt nor2 NOR-A1 NOR-D1 NOR-B1 wn=0.35u wp=1u t=0.5u $未优化尺寸系数S3mn2 NOR-D1 NOR-B1 gnd gnd NCH l=0.2u w=wn ad='wn*t' pd='wn+2*t' as='wn*t' ps='wn+2*t'mn1 NOR-D1 NOR-A1 gnd gnd NCH l=0.2u w=wn ad='wn*t' pd='wn+2*t' as='wn*t' ps='wn+2*t'mp1 NOR-S1 NOR-A1 vdd vdd PCH l=0.2u w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'mp2 NOR-D1 NOR-B1 NOR-S1 vdd PCH l=0.2u w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'.ends.subckt inv2 in out wn='0.35u*2.6' wp='1u*2.6' t=0.5u $优化尺*.subckt inv2 in out wn=0.35u wp=1u t=0.5u $未优化尺寸系数S4mn out in gnd gnd NCH l=0.2u w=wn ad='wn*t' pd='wn+2*t' as='wn*t' ps='wn+2*t'mp out in vdd vdd PCH l=0.2u w=wp ad='wp*t' pd='wp+2*t' as='wp*t' ps='wp+2*t'.endsX1 vin 2 inv1X2 2 3 vdd vdd nand3X3 3 4 gnd nor2X4 4 vout inv2.op.tran 5p 3000p.meas tran voutmax max v(vout) from=5p to=3000p.meas tran voutmin min v(vout) from=5p to=3000p.meas tran tphl+trig v(vin)+val=0.9+rise=2+targ v(vout)+val='0.5*(voutmax-voutmin)+voutmin'.meas tran tplh+trig v(vin)+val=0.9+fall=2+targ v(vout)+val='0.5*(voutmax-voutmin)+voutmin'+fall=2.end$Cg1=2.46fF，所以负载为12.3fF仿真结果如下：尺寸系数全部优化得到的tphl和tplh尺寸系数全部未优化得到的tphl和tplhVout对比图：粉线是尺寸系数全部未优化、浅蓝线是尺寸系数未优化的输出电压、绿线是输入电压波形；..从结果上来看，未优化的tphl和tplh均比优化过的tphl和tplh值要小几十个ps,所以计算得到的尺寸系数是有效的减少了总的延时时间。