Verification Test bench Setup
RTL update Timing Constrain 1st version Netlist Layout RTL Synthesize
RTL Stimulation
Netlist Stimulation
SDF file Back Timing Check Final version Netlist Layout RTL Synthesize
3 weeks
Fix cell Yes
2 weeks
Fix clk Fix Wire Final sdf to Cx No GDS to Layout
No
This phase is about 2 Weeks.
Project Assign
GDS check and tapeout Process Flow
3
Chip Sells and Technical Support Cost
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Project Design Cost
L Engineer Cost Layout Engineer Cost
Project Design Cost
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Cost Analyze
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Project Design Flow
Project
Design
RTL design, Function Verification And Stimulation, Synthesize, FPGA test, Firmware.
Cost Item
design Engineer Cost
Cost
About 200 person*week About 6 person*week Cost $25,000
Comment
Half Senior engineer
layout Engineer Cost
Spec Group License Cost
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Production Cost
The wafe price is $1400 {8 inch wafe, tatal area = 3.14* (25.4*4)*(25.4*4) = 32413mm*mm) The wafe using rate is about 80%. the Chip wafe price is: 1400 * 6.25 / (32413 * 80%) = $0.34 / pcs the Chip test cost price is $0.10 / pcs the Chip package price is $0.10 / pcs the chip Yield Rate is 90% ------------------------------------------------------------The total of chip production price is (0.34 + 0.10 + 0.10)/0.9 = $0.60
Addition IP License Cost
NA FPGA board, Agilent Test Tool, PCB board $35,000 TSMC013LV process
LOGO Design and Test Cost Chip MPW Cost
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AP software (player)
NA
0%
EE Soluation
6
person*week
3%
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Cost Analyze
1
Project Design Cost (MPW)
2
Chip Production Cost (Full Mask)
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Production Cost
TSMC Full Mask and Wafer Cost
Chip Production Cost
Addition IP License Chip Test Cost Chip Package Cost Chip Yield Rate Cost
DRC
LVS
ERCMT FormFra bibliotekChip Tapeout
Project Schedule Flow
Engineer Source EES: about 4 weeks EES
Design Engineer: 4 EES Engineer: 1
EES
EES
Design
Design
Design FPGA TSMC MPW
Verification Engineer: 6
FPGA test
Verification Verification Verification
PCB Engineer: 1
PCB MPW: 8 weeks
Time
16 weeks
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Spec Group License Cost Addition IP License Cost Design and Test Cost Chip MPW Cost
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Project Design Cost
MPW
PCB Demo Board
Verification Flow
Total about 18 weeks 1 week 2 weeks 2~4 weeks 10 weeks
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2 weeks
Prepare Library data Netlist IN
SDF file Stimulation
FPGA Synthesize
PCB FPGA Test Board
FPGA test (Include Firmware) SDF file Stimulation
PCB Receiver Board
Timing Check Final SDF file Back
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Project Engineer Resource
Item Source percentage 37%
Design
73
person*week
Verification
100 person*week
50%
FPGA
16
persion*week
8%
Firmware
5
persion*week
2.50%
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Contents
1 2 3 4
Project Design Flow
Project Schedule Flow
Engineer Resource
Netlist to GDS Process Flow
2 days
Add Scan Chain Fix Time Floorplaning IO Planning, Power Ring mesh rail Planning Macro Planning No
Check PPA list name ,match with Netlist PAD (Name, Size)
TSMC130nm process
Addition IP License
$ / wafer
Chip Test Cost
$0.10 / pcs chip
Chip Package Cost
$0.10 / pcs chip
Chip Yield Rate Cost
Target 90%
After package
Design BOM APR2Layout Request Form
Library Verification
STD IO Memory Library
Chip Try run
Pin_location.txt
APR GDS to Layout
Final Chip Verification
Chip Information
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Production Cost
Cost Item Cost Comment
TSMC Full Mask and Wafer Cost
Full Mask $300000 Wafer $1400/wafer