5.5 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU timers (Figure 31) (TIMER0/1/2).

CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for DSP/BIOS.

If the application is not using DSP/BIOS, then Timer 2 can be used in the application.

The CPU-timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 32.

[1]. 三个定时器0、1、2，32位

[2]. 0、1可随用户任意使用，2专为DSP/BIOS模式预备（当不启用DSP/BIOS模式时可以随

意定义定时器2）

The general operation of the CPU timer is as follows: The 32-bit counter register TIMH:TIM is

loaded with the value in the period register PRDH:PRD. The counter decrements once every

(TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles where TDDRH:TDDR is the timer divider. When the

counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers

listed in Table 31 are used to configure the timers.

[1]. 定时器配置流程：32位计数寄存器TIMH||TIM将PRDH||PRD中的值载入；

[2]. 每[TDDRH||TDDR]+1个系统时钟，计数寄存器都递减一次。

[3]. 当计数器为0时，发起一次定时中断。

[1]. TIMH||TIM在两种情况下从PRDH||PRD中加载初值：

a) TIMH||TM值减为0时

b) TCR寄存器的TRB位置一时

[1]. TPR寄存器是定时器自身时钟的设置模块儿

[2]. 高八位从低八位读取数据，高八位是只读位。在归零后或者TRB位置一后，从低八位

读取数据

定时器控制寄存器