ISO7640GND2GND2OUTAOUTCOUTBENOUTDV VCC2GND2GND2OUTAOUTCOUTBINDEN2V VCC2ISO7641ISO7640FMISO7641FM SLLSE89D–SEPTEMBER2011–REVISED JULY2012Low Power Quad Channels Digital IsolatorsCheck for Samples:ISO7640FM,ISO7641FMFEATURES APPLICATIONS•Signaling Rate:150Mbps•Optocoupler Replacement in:•Low Power Consumption,Typical I CC per–Industrial FieldbusChannel(3.3V Supplies):–Profibus–ISO7640FM:2mA at25Mbps–Modbus–ISO7641FM:2.4mA at25Mbps–DeviceNet TM Data Buses•Low Propagation Delay:7ns Typical–Servo Control Interface•Output Defaults to Low-state in fail-safe mode–Motor Control•Wide Temperature Range:–40°C to125°C–Power Supplies•50KV/µs Transient Immunity,Typical–Battery Packs•Long Life with SiO2Isolation barrierSAFETY AND REGULATORY•Operates From2.7V,3.3V and5V Supply andAPPROVALSLogic Levels•6000V PK/4243V RMS for1Minute per UL1577•Wide Body SOIC-16Package(approved)•VDE Approval for DIN EN60747-5-2(VDE0884Rev.2),1414V PK Working Voltage(approved)•CSA Component Acceptance Notice5A,IEC60601-1Medical Standard(approved)•5KV RMS Reinforced Insulation per TUV forEN/UL/CSA60950-1and EN/UL/CSA61010-1(approved)DESCRIPTIONISO7640FM and ISO7641FM provide galvanic isolation up to6KV PK for1minute per UL and VDE.These devices are also certified up to5KV RMS Reinforced isolation at a working voltage of400V RMS per end equipment standards EN/UL/CSA60950-1and61010-1.ISO7640F and ISO7641F are quad channel isolators;ISO7640F has four forward and ISO7641F has three forward and one reverse direction channels.Suffix F indicates that output defaults to Low-state in fail-safe conditions(see Table1).M-Grade devices are high speed isolators capable of150Mbps data rate with fast propagation delaysPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.UNLESS OTHERWISE NOTED this document contains Copyright©2011–2012,Texas Instruments Incorporated PRODUCTION DATA information current as of publication date.捷多邦，您值得信赖的PCB打样专家！ISO7640FMISO7641FMSLLSE89D–SEPTEMBER2011–REVISED These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.DESCRIPTION CONTINUEDEach isolation channel has a logic input and output buffer separated by a silicon dioxide(SiO2)insulation barrier. Used in conjunction with isolated power supplies,these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.The devices have TTL input thresholds and can operate from2.7V,3.3V and5V supplies.All inputs are5V tolerant when supplied from3.3V or2.7V supplies.PIN DESCRIPTIONSPINI/O DESCRIPTIONNAME ISO7640ISO7641INA33I Input,channel AINB44I Input,channel BINC55I Input,channel CIND611I Input,channel DOUTA1414O Output,channel AOUTB1313O Output,channel BOUTC1212O Output,channel COUTD116O Output,channel DEnables(when input is High or Open)or Disables(when input is Low)OUTA,OUTB,OUTC EN10-Iand OUTD of ISO7640EN1-7I Enables(when input is High or Open)or Disables(when input is Low)OUTD of ISO7641Enables(when input is High or Open)or Disables(when input is Low)OUTA,OUTB,andEN2-10IOUTC of ISO7641V CC111–Power supply,V CC1V CC21616–Power supply,V CC2GND12,82,8–Ground connection for V CC1GND29,159,15–Ground connection for V CC2NC7--No Connect pins are floating with no internal connectionTable1.FUNCTION TABLE(1)INPUT OUTPUT INPUT OUTPUT ENABLE OUTPUTV CC V CC(INx)(ENx)(OUTx)H H or Open HL H or Open LPU PUX L ZOpen H or Open LPD PU X H or Open LPD PU X L ZPU PD X X Z(1)PU=Powered Up(V CC≥2.7V);PD=Powered Down(V CC≤2.1V);X=Irrelevant;H=High Level;L=Low Level;Z=High Impedance2Submit Documentation Feedback Copyright©2011–2012,Texas Instruments IncorporatedISO7640FMISO7641FM SLLSE89D–SEPTEMBER2011–REVISED JULY2012AVAILABLE OPTIONSRATED INPUT DATA RATE CHANNEL MARKED ORDERING PRODUCT PACKAGEISOLATION THRESHOLD and FILTER DIRECTION AS NUMBERISO7640FMDW(rail)4Forward,ISO7640FM ISO7640FM0Reverse1.5V TTL ISO7640FMDWR(reel)6KV PK/150Mbps,DW-16(CMOS5KV RMS(1)No Noise Filter ISO7641FMDW(rail)Compatible)3Forward,ISO7641FM ISO7641FM1Reverse ISO7641FMDWR(reel) (1)See the Regulatory Information table for detailed isolation ratings.ABSOLUTE MAXIMUM RATINGS(1)VALUE PARAMETER UNITMIN MAXSupply voltage(2)V CC1,V CC2–0.56VVoltage INx,OUTx,ENx–0.56VOutput Current,I O±15mAHuman Body Model ESDA,JEDEC JS-001-2012±4kVField-Induced Charged DeviceElectrostatic discharge JEDEC JESD22-C101E All pins±1.5kV ModelMachine Model JEDEC JESD22-A115-A±200VMaximum junction temperature,T J150°CStorage temperature,T STG-65150°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)All voltage values except differential I/O bus voltages are with respect to the local ground terminal(GND1or GND2)and are peakvoltage values.RECOMMENDED OPERATING CONDITIONSPARAMETER MIN TYP MAX UNITSupply voltage V CC1,V CC2 2.7 5.5VHigh-level output current I OH-4mALow-level output current I OL4mAHigh-level input voltage V IH2V CC VLow-level input voltage V IL00.8V≥3V-Operation 6.67Input pulse duration t ui ns<3V-Operation10≥3V-Operation0150Signaling rate1/t ui Mbps<3V-Operation0100Junction temperature T J-40136°CAmbient temperature T A-4025125°C Copyright©2011–2012,Texas Instruments Incorporated Submit Documentation Feedback3ISO7640FMISO7641FMSLLSE89D–SEPTEMBER2011–REVISED THERMAL INFORMATIONISO76xxTHERMAL METRIC(1)UNITSDW(16Pins)θJA Junction-to-ambient thermal resistance72θJC(top)Junction-to-case(top)thermal resistance38θJB Junction-to-board thermal resistance39°C/WψJT Junction-to-top characterization parameter9.4ψJB Junction-to-board characterization parameter n/aθJC(bottom)Junction-to-case(bottom)thermal resistance n/aV CC1=V CC2=5.5V,T J=150°C,C L=15pFP D Maximum Device Power Dissipation399mWInput a75MHz50%duty cycle square wave(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953. ELECTRICAL CHARACTERISTICSV CC1and V CC2at5V±10%(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITI OH=–4mA;see Figure1V CCx(1)–0.8 4.8V OH High-level output voltage VI OH=–20μA;see Figure1V CCx(1)–0.15I OL=4mA;see Figure10.20.4V OL Low-level output voltage VI OL=20μA;see Figure100.1V I(HYS)Input threshold voltage hysteresis450mVI IH High-level input current V IH=V CC at INx or ENx10μAI IL Low-level input current V IL=0V at INx or ENx-10CMTI Common-mode transient immunity V I=V CC or0V;see Figure42575kV/μs (1)V CCx is the supply voltage,V CC1or V CC2,for the output channel that is being measured.SWITCHING CHARACTERISTICSV CC1and V CC2at5V±10%(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITt PLH,t PHL Propagation delay time 3.5710.5See Figure1PWD(1)Pulse width distortion|t PHL–t PLH|2Same-direction Channels2nst sk(o)(2)Channel-to-channel output skew timeOpposite-direction Channels3t sk(pp)(3)Part-to-part skew time 4.5t r Output signal rise time 1.6See Figure1nst f Output signal fall time1Disable Propagation Delay,high-to-hight PHZ516 impedance outputDisable Propagation Delay,low-to-hight PLZ516 impedance outputSee Figure2ns Enable Propagation Delay,high impedance-to-t PZH416 high outputEnable Propagation Delay,high impedance-to-t PZL416 low outputFail-safe output delay time from input data ort fs See Figure39.5μs power loss(1)Also known as Pulse Skew.(2)t sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the samedirection while driving identical loads.(3)t sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the samedirection while operating at identical supply voltages,temperature,input signals and loads.4Submit Documentation Feedback Copyright©2011–2012,Texas Instruments IncorporatedISO7640FMISO7641FM SLLSE89D–SEPTEMBER2011–REVISED JULY2012 SUPPLY CURRENTV CC1and V CC2at5V±10%(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISO7640FMI CC10.6 1.2Disable EN=0VI CC2 4.5 6.6I CC10.7 1.3DC to1MbpsI CC2 4.6 6.7I CC1 1.1210Mbps mADC Signal:V I=V CC or0V,I CC2 6.610.5AC Signal:All channels switching with square wave clockI CC1 1.93input;C L=15pF25MbpsI CC29.714.7I CC18.214.5150MbpsI CC23558ISO7641FMI CC1 2.6 4.2Disable EN1=EN2=0VI CC2 4.2 6.8I CC1 2.7 4.3DC to1MbpsI CC2 4.3 6.9I CC1 3.6 4.910Mbps mADC Signal:V I=V CC or0V,I CC268.2AC Signal:All channels switching with square wave clockI CC1 5.1 6.6input;C L=15pF25MbpsI CC28.811.4I CC11722150MbpsI CC23142Copyright©2011–2012,Texas Instruments Incorporated Submit Documentation Feedback5ISO7640FMISO7641FMSLLSE89D–SEPTEMBER2011–REVISED ELECTRICAL CHARACTERISTICSV CC1at5V±10%and V CC2at3.3V±10%(over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITI OH=–4mA;see OUTx on V CC1(5V)side V CC1–0.8 4.8Figure1OUTx on V CC2(3.3V)side V CC2-0.43V OH High-level output voltage VI OH=–20μA;see OUTx on V CC1(5V)side V CC1–0.15Figure1OUTx on V CC2(3.3V)side V CC2–0.1 3.3I OL=4mA;see Figure10.20.4V OL Low-level output voltage VI OL=20μA;see Figure100.1V I(HYS)Input threshold voltage430mV hysteresisI IH High-level input current V IH=V CC at INx or ENx10μAI IL Low-level input current V IL=0V at INx or ENx-10Common-mode transientCMTI V I=V CC or0V;see Figure42550kV/μs immunitySWITCHING CHARACTERISTICSV CC1at5V±10%and V CC2at3.3V±10%(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITt PLH,t PHL Propagation delay time4813See Figure1PWD(1)Pulse width distortion|t PHL–t PLH|2Same-direction Channels 2.5nst sk(o)(2)Channel-to-channel output skew timeOpposite-direction Channels 3.5t sk(pp)(3)Part-to-part skew time6t r Output signal rise time2See Figure1nst f Output signal fall time 1.2Disable Propagation Delay,high-to-hight PHZ 6.517 impedance outputDisable Propagation Delay,low-to-hight PLZ 6.517 impedance outputSee Figure2ns Enable Propagation Delay,high impedance-to-t PZH 5.517 high outputEnable Propagation Delay,high impedance-to-t PZL 5.517 low outputFail-safe output delay time from input data ort fs See Figure39.5μs power loss(1)Also known as Pulse Skew.(2)t sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the samedirection while driving identical loads.(3)t sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the samedirection while operating at identical supply voltages,temperature,input signals and loads.6Submit Documentation Feedback Copyright©2011–2012,Texas Instruments IncorporatedISO7640FMISO7641FM SLLSE89D–SEPTEMBER2011–REVISED JULY2012 SUPPLY CURRENTV CC1at5V±10%and V CC2at3.3V±10%(over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISO7640FMI CC10.6 1.2Disable EN=0VI CC2 3.6 5.1I CC10.7 1.3DC to1MbpsI CC2 3.7 5.2I CC1 1.1210Mbps mADC Signal:V I=V CC or0V,I CC257.1AC Signal:All channels switching with square wave clock input;C LI CC1 1.93=15pF25MbpsI CC2 6.911I CC18.214.5150MbpsI CC22440ISO7641FMI CC1 2.6 4.2Disable EN1=EN2=0VI CC2 3.2 4.9I CC1 2.7 4.3DC to1MbpsI CC2 3.35I CC1 3.6 4.910Mbps mADC Signal:V I=V CC or0V,I CC2 4.4 5.8AC Signal:All channels switching with square wave clock input;C LI CC1 5.1 6.6=15pF25MbpsI CC2 6.17.6I CC11722150MbpsI CC220.626.5Copyright©2011–2012,Texas Instruments Incorporated Submit Documentation Feedback7ISO7640FMISO7641FMSLLSE89D–SEPTEMBER2011–REVISED ELECTRICAL CHARACTERISTICSV CC1at3.3V±10%and V CC2at5V±10%(over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITI OH=–4mA;see Figure1OUTx on V CC1(3.3V)side V CC1–0.43OUTx on V CC2(5V)side V CC2–0.8 4.8V OH High-level output voltage VI OH=–20μA;see Figure1OUTx on V CC1(3.3V)side V CC1–0.1 3.3OUTx on V CC2(5V)side V CC2–0.15I OL=4mA;see Figure10.20.4V OL Low-level output voltage VI OL=20μA;see Figure100.1V I(HYS)Input threshold voltage hysteresis430mVI IH High-level input current V IH=V CC at INx or ENx10μAI IL Low-level input current V IL=0V at INx or ENx-10CMTI Common-mode transient immunity V I=V CC or0V;see Figure42550kV/μs SWITCHING CHARACTERISTICSV CC1at3.3V±10%and V CC2at5V±10%(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITt PLH,t PHL Propagation delay time47.512.5See Figure1PWD(1)Pulse width distortion|t PHL–t PLH|2Same-direction Channels 2.5nst sk(o)(2)Channel-to-channel output skew timeOpposite-direction Channels 3.5t sk(pp)(3)Part-to-part skew time6t r Output signal rise time 1.7See Figure1nst f Output signal fall time 1.1Disable Propagation Delay,high-to-high impedancet PHZ 5.517 outputDisable Propagation Delay,low-to-high impedancet PLZ 5.517 outputSee Figure2ns Enable Propagation Delay,high impedance-to-hight PZH 4.517 outputEnable Propagation Delay,high impedance-to-lowt PZL 4.517 outputFail-safe output delay time from input data or powert fs See Figure39.5μs loss(1)Also known as Pulse Skew.(2)t sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the samedirection while driving identical loads.(3)t sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the samedirection while operating at identical supply voltages,temperature,input signals and loads.8Submit Documentation Feedback Copyright©2011–2012,Texas Instruments IncorporatedISO7640FMISO7641FM SLLSE89D–SEPTEMBER2011–REVISED JULY2012 SUPPLY CURRENTV CC1at3.3V±10%and V CC2at5V±10%(over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISO7640FMI CC10.350.7Disable EN=0VI CC2 4.5 6.6I CC10.40.8DC to1MbpsI CC2 4.6 6.7I CC10.7 1.210Mbps mADC Signal:V I=V CC or0V,I CC2 6.610.5AC Signal:All channels switching with square wave clock input;C L=I CC1 1.1215pF25MbpsI CC29.714.7I CC158.5150MbpsI CC23558ISO7641FMI CC1 1.9 2.9Disable EN1=EN2=0VI CC2 4.2 6.8I CC123DC to1MbpsI CC2 4.3 6.9I CC1 2.5 3.510Mbps mADC Signal:V I=V CC or0V,I CC268.2AC Signal:All channels switching with square wave clock input;C L=I CC1 3.4 4.515pF25MbpsI CC28.811.4I CC110.514.5150MbpsI CC23142Copyright©2011–2012,Texas Instruments Incorporated Submit Documentation Feedback9ISO7640FMISO7641FMSLLSE89D–SEPTEMBER2011–REVISED ELECTRICAL CHARACTERISTICSV CC1and V CC2at3.3V±10%(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITI OH=–4mA;see Figure1V CCx(1)–0.43V OH High-level output voltage VI OH=–20μA;see Figure1V CCx(1)–0.1 3.3I OL=4mA;see Figure10.20.4V OL Low-level output voltage VI OL=20μA;see Figure100.1V I(HYS)Input threshold voltage425mV hysteresisI IH High-level input current V IH=V CC at INx or ENx10μAI IL Low-level input current V IL=0V at INx or ENx-10Common-mode transientCMTI V I=V CC or0V;see Figure42550kV/μs immunity(1)V CCx is the supply voltage,V CC1or V CC2,for the output channel that is being measured.SWITCHING CHARACTERISTICSV CC1and V CC2at3.3V±10%(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITt PLH,t PHL Propagation delay time48.514See Figure1PWD(1)Pulse width distortion|t PHL–t PLH|2Same-direction Channels3nst sk(o)(2)Channel-to-channel output skew timeOpposite-direction Channels4t sk(pp)(3)Part-to-part skew time 6.5t r Output signal rise time2See Figure1nst f Output signal fall time 1.3Disable Propagation Delay,high-to-hight PHZ 6.517 impedance outputDisable Propagation Delay,low-to-high impedancet PLZ 6.517 outputSee Figure2ns Enable Propagation Delay,high impedance-to-hight PZH 5.517 outputEnable Propagation Delay,high impedance-to-lowt PZL 5.517 outputFail-safe output delay time from input data ort fs See Figure39.2μs power loss(1)Also known as Pulse Skew.(2)t sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the samedirection while driving identical loads.(3)t sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the samedirection while operating at identical supply voltages,temperature,input signals and loads.10Submit Documentation Feedback Copyright©2011–2012,Texas Instruments IncorporatedSUPPLY CURRENTV CC1and V CC2at3.3V±10%(over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISO7640FMI CC10.350.7Disable EN=0VI CC2 3.6 5.1I CC10.40.8DC to1MbpsI CC2 3.7 5.2I CC10.7 1.210Mbps mADC Signal:V I=V CC or0V,I CC257.1AC Signal:All channels switching with square wave clock input;C L=I CC1 1.1215pF25MbpsI CC2 6.911I CC158.5150MbpsI CC22440ISO7641FMI CC1 1.9 2.9Disable EN1=EN2=0VI CC2 3.2 4.9I CC123DC to1MbpsI CC2 3.35I CC1 2.5 3.510Mbps mADC Signal:V I=V CC or0V,I CC2 4.4 5.8AC Signal:All channels switching with square wave clock input;C L=I CC1 3.4 4.515pF25MbpsI CC2 6.17.6I CC110.514.5150MbpsI CC220.626.5ELECTRICAL CHARACTERISTICSV CC1and V CC2at2.7V(1)(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITI OH=–4mA;see Figure1V CC(2)–0.5 2.4V OH High-level output voltage VI OH=–20μA;see Figure1V CC(2)–0.1 2.7I OL=4mA;see Figure10.20.4V OL Low-level output voltage VI OL=20μA;see Figure100.1V I(HYS)Input threshold voltage hysteresis350mVI IH High-level input current V IH=V CC at INx or ENx10μA I IL Low-level input current V IL=0V at INx or ENx-10CMTI Common-mode transient immunity V I=V CC or0V;see Figure42550kV/μs(1)For2.7V-operation,max data rate is100Mbps.(2)V CCx is the supply voltage,V CC1or V CC2,for the output channel that is being measured.SWITCHING CHARACTERISTICSV CC1and V CC2at2.7V(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITt PLH,t PHL Propagation delay time5816See Figure1PWD(1)Pulse width distortion|t PHL–t PLH| 2.5Same-direction Channels4ns t sk(o)(2)Channel-to-channel output skew timeOpposite-direction Channels5t sk(pp)(3)Part-to-part skew time8t r Output signal rise time 2.3See Figure1ns t f Output signal fall time 1.8Disable Propagation Delay,high-to-hight PHZ818 impedance outputDisable Propagation Delay,low-to-hight PLZ818 impedance outputSee Figure2ns Enable Propagation Delay,high impedance-to-t PZH718 high outputEnable Propagation Delay,high impedance-to-t PZL718 low outputFail-safe output delay time from input data ort fs See Figure38.5μs power loss(1)Also known as Pulse Skew.(2)t sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the samedirection while driving identical loads.(3)t sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the samedirection while operating at identical supply voltages,temperature,input signals and loads.SUPPLY CURRENTV CC1and V CC2at2.7V(over recommended operating conditions unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISO7640FMI CC10.20.6Disable EN=0VI CC2 3.35I CC10.20.7DC to1MbpsI CC2 3.4 5.1I CC10.4 1.110Mbps mADC Signal:V I=V CC or0V,I CC2 4.4 6.8AC Signal:All channels switching with square wave clock input;C L=I CC10.8 1.815pF25MbpsI CC269.5I CC1 2.75100MbpsI CC214.221ISO7641FMI CC1 1.6 2.4Disable EN1=EN2=0VI CC2 2.8 4.1I CC1 1.7 2.5DC to1MbpsI CC2 2.9 4.2I CC1 2.1310Mbps mADC Signal:V I=V CC or0V,I CC2 3.85AC Signal:All channels switching with square wave clock input;C L=I CC1 2.8 3.815pF25MbpsI CC2 5.2 6.7I CC1 6.47.5100MbpsI CC211.815.5V OV VL =1kW 1%±VVOHCCCC OLC L BOH CC1OLPARAMETER MEASUREMENT INFORMATIONA.The input pulse is supplied by a generator having the following characteristics:PRR ≤50kHz,50%duty cycle,t r ≤3ns,t f ≤3ns,Z O =50Ω.At the input,50Ωresistor is required to terminate Input Generator signal.It is not needed in actual application.B.C L =15pF and includes instrumentation and fixture capacitance within ±20%.Figure 1.Switching Characteristics Test Circuit and Voltage WaveformsA.The input pulse is supplied by a generator having the following characteristics:PRR ≤10kHz,50%duty cycle,t r ≤3ns,t f ≤3ns,Z O =50Ω.B.C L =15pF and includes instrumentation and fixture capacitance within ±20%.Figure 2.Enable/Disable Propagation Delay Time Test Circuit and Waveform–OLV OAV I IN = V CC0V CCVOLV OHPARAMETER MEASUREMENT INFORMATION (continued)A.C L =15pF and includes instrumentation and fixture capacitance within ±20%.Figure 3.Failsafe Delay Time Test Circuit and Voltage WaveformsA.C L =15pF and includes instrumentation and fixture capacitance within ±20%.Figure mon-Mode Transient Immunity Test CircuitDEVICE INFORMATIONIEC INSULATION AND SAFETY-RELATED SPECIFICATIONS FOR DW-16PACKAGEPARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01)Minimum air gap(Clearance)Shortest terminal to terminal distance through air8.3mm Minimum external tracking Shortest terminal to terminal distance across theL(I02)(1)8.1mm (Creepage)package surfaceTracking resistance(ComparativeCTI DIN IEC60112/VDE0303Part1≥400V Tracking Index)Minimum Internal Gap(InternalDistance through the insulation0.014mm Clearance)V IO=500V,T A<100°C>1012 Isolation resistance,Input toR IO(2)ΩOutput V=500V,100°C≤T A≤max>1011IOBarrier capacitance,Input to V I=0.4sin(2πft),f=1MHzC IO(2)2pFOutputC I(3)Input capacitance V I=V CC/2+0.4sin(2πft),f=1MHz,V CC=5V2pF(1)Per JEDEC package dimensions.(2)All pins on each side of the barrier tied together creating a two-terminal device.(3)Measured from input pin to ground.NOTECreepage and clearance requirements should be applied according to the specificequipment isolation standards of an application.Care should be taken to maintain thecreepage and clearance distance of a board design to ensure that the mounting pads ofthe isolator on the printed circuit board do not reduce this distance.Creepage and clearance on a printed circuit board become equal according to themeasurement techniques shown in the Isolation Glossary.Techniques such as insertinggrooves and/or ribs on a printed circuit board are used to help increase thesespecifications.DIN EN60747-5-2(VDE0884TEIL2)INSULATION CHARACTERISTICS(4)over recommended operating conditions(unless otherwise noted)PARAMETER TEST CONDITIONS SPECIFICATION UNIT V IORM Maximum working insulation voltage(1)1414V PEAKAfter Input/Output safety test subgroup2/3,V PR=V IORM x1.2,t=10s,1697Partial discharge<5pCMethod a,After environmental tests subgroup1,V PR Input-to-output test voltage V PR=V IORM x1.6,t=10s,2262V PEAKPartial Discharge<5pCMethod b1,100%Production testV PR=V IORM x1.875,t=1s2652Partial discharge<5pCV TEST=V IOTMV IOTM Maximum transient overvoltage t=60sec(Qualification)6000V PEAKt=1sec(100%Production)R S Insulation resistance V IO=500V at T S>109ΩPollution degree2(4)Climatic Classification40/125/21(1)For applications that require DC working voltages between GND1and GND2,please contact Texas Instruments for further details.IEC60664-1RATINGS TABLEPARAMETER TEST CONDITIONS SPECIFICATIONBasic Isolation Group Material Group IIRated mains voltage≤300V RMS I–IVInstallation classification Rated mains voltage≤600V RMS I–IIIRated mains voltage≤1000V RMS I–II REGULATORY INFORMATIONVDE TUV CSA ULCertified according to DIN EN Certified according to Approved under CSA Component Recognized under1577Component 60747-5-2EN/UL/CSA60950-1and61010-Acceptance Notice#5A Recognition Program1Basic Insulation5000V RMS Reinforced Insulation,5000V RMS Reinforced InsulationMaximum Transient400V RMS maximum working2Means of Patient Protection atOvervoltage,6000V PK voltage Single Protection,4243V RMS(1)125V RMS per IEC60601-1(3rdMaximum Working Voltage,5000V RMS Basic Insulation,600Ed.)1414V PK V RMS maximum working voltageFile Number:40016131Certificate Number:U8V1108File Number:220991File Number:E18197477311005(1)Production tested≥5092V RMS for1second in accordance with UL1577.IEC SAFETY LIMITING VALUESSafety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.A failure of the IO can allow low resistance to ground or the supply and,without current limiting,dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.PARAMETER TEST CONDITIONS MIN TYP MAX UNITθJA=72°C/W,V I=5.5V,T J=150°C,T A=25°C316 Safety input,output,or supplyI S DW-16θJA=72°C/W,V I=3.6V,T J=150°C,T A=25°C482mAcurrentθJA=72°C/W,V I=2.7V,T J=150°C,T A=25°C643T S Maximum case temperature150°C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table.The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature.The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages.The power is the recommended maximum input voltage times the current.The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.。