reg clk,rst; reg[10:0] data; wire z,x;
assign x=data[10]; always #10 clk = ~clk;
always @(posedge clk) data<={data[9:0],data[10]};
initial begin clk=0; rst=0; #2 rst=1; #30 rst=0; data ='b1010_1001_00; #500 $stop; end
reg [2:1] state; reg [2:1] next_state; always @(posedge clk)
if (rst) state <= S0; else state< = next_state;
assign Z = (state == S2);
always @(state or X) case (state)
有限输入串的识别器
设计要求：有限输入串的识别器 一个输入端 (X) 和一个输出端 (Z) 如果上次复位之后输入没有观察到…100…序列，那么只要 在输入端检测到…010…的输入序列，输出端即为1
步骤1: 理解说明 最好写出一些输入样本和输出行为:
X: 0 0 1 0 1 0 1 0 0 1 0 … Z: 0 0 0 1 0 1 0 1 0 0 0 …
S4: if (X) next_state = S4 ; else next_state = S5;
S5: if (X) next_state = S2 ; else next_state = S6;
S6: next_state = S6; default: next_state = S0;
endcase endmodule
有限输入串的识别器
包括状态分配（或状态编码）的Verilog描述
module string1 (clk, X, rst, Z); input clk, X, rst; output Z;
parameter S0 = 3'b000, S1= 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110;
VIII - Working with Sequential
Logic
© Copyright 2004, Gaetano Borriello and Randy H. Katz
5
有限输入串的识别器（测试程序）
`timescale 1ns/1ns `include "./seq.v" module seqdet_Top;
步骤2: 画状态图
假设用摩尔机实现
先画出其必须识别的串010 和 100
只有一个输入，则每个状态应 该有两个分支
reset
0 S1 [0] 1
S0 [0]
1
S4 [0]
0
S2
S5
[0]
[0]
0
0
S3
S6
[1]
[0]
0 or 1
VIII - Working with Sequential
string1 m(clk,x,rst,z);
endmodule
VIII - Working with Sequential
Logic
© Copyright 2004, Gaetano Borriello and Randy H. Katz
S0: if (X) next_state = S4 ; else next_state = S1;
S1: if (X) next_state = S2; else next_state = S1;
S2: if (X) next_state = S4 ; else next_state = S3;
S3: if (X) next_state = S2 ; else next_state = S6;
S3 ...010 [1]
© Copyright 2004, Gaetano Borriello and Randy H. Katz
S6 ...100 [0]
0 or 1
3
有限输入串的识别器
S2和S5仍然是不完整的条件
S2= …01; 如果下一个输入为
1,就不再是010序列的前缀而 成为终止序列的前缀(01)1(00) S4 就是代表这种情况
Logic
© Copyright 2004, Gaetano Borriello and Randy H. Katz
2
有限输入串的识别器
离开状态S3条件: 已经识别到 …010序列
如果下一位输入为0，那么状态机已经接收到…100 (终 止)，到状态 S6，即终止循环状态
如果下一位输入为1，则状态机接收序列
X: 1 1 0 1 1 0 1 0 0 1 0 … Z: 0 0 0 0 0 0 0 1 0 0 0 …
VIII - Working with Sequential
Logic
© Copyright 2004, Gaetano Borriello and Randy H. Katz
1
有限输入串的识别器
reset
S0
[0]
0
1
S5 =…10;如果下一个输入为1, 0 则接收机的序列为101，可能 为序列010的前缀，S2就是代
S1
S4
1
[0] ...0 ...1 [0]
11
0
01
1 S5 [0]...10
0
寻找相同的意思
最小的状态使代表状态的位数 可以尽可能少
S3 ...010 [1]
S6 ...100 [0]
0 or 1
一旦所有状态有完整的条件转换， 意味着是一个最终状态图
VIII - Working with Sequential
Logic
© Copyright 2004, Gaetano Borriello and Randy H. Katz
4
为…0101 ， …01 (状态S2)
reset
S0
状态S1条件: S1表示在接收
[0]
0
1
到1之前的…0序列
0
S1
S4
1
只要输入为0就会在此循环
[0] ...0 ...1 [0]
1
0
状态S4条件: S4描述连1序列的状态
S2
S5
...01 [0]
[0]
只要输入为1就会在此循环
01
0
VIII - Working with Sequential Logic