North Bridge VT82C501
Host Address Bus
Host Date Bus
168pins unbuffer SDRAM module
HDD
CDROM
USB PORT
South Bridge VT82C686
PCI Device
ISA Bus
PCI slots
COM PORT
HWQA
培訓教材
之硬體架构篇
Inventec Confidential 2020/4/7
1
M/B HARDWARE DESCRIPTION • PC hardware architecture • Signal integrity description • Circuit design concept • PCI bus • Cache • IC pack mode
Hub
Firmware Hub
PCI BUS
PCI DEVICE
PCI Slots
(Example 2) 3
PC hardware architecture . GMCH: Graphics & memory controller hub . ICH: I/O controller hub. With PCI & LPC
Processor
PPGA 370
+
128K Cache
2.5V,2V,1.8V
U6
Graphics and Memory
Controller Hub
Intel FW82810DC100
3.3V,1.8V
C PU C LK 66M
Hos t C LK 66M X5
SD R A M C LK 100M X8
66/100MHZ
DIMM
North Bridge
AGP BUS
VGA CTRL
MTR
VIDEO SGRAM
33MHZ
66/100MHZ
South Bridge
PCI SLOTS
SUPER I/O CTRL
ISA DRIVE
ISA SLOT1
(Example 1)
ISA SLOT2
33MHZ
HWQA培訓教材
6
PC hardware architecture III. DMA channels
Two DMA controllers DMA channel 0: 8-bit DMA channel 1: 8-bit DMA channel 2: 8-bit, FDC DMA channel 3: 8-bit DMA channel 4: Cascaded DMA channel 5: 16-bit DMA channel 6: 16-bit DMA channel 7: 16-bit
interface. . FWH: Firmware hub. . LPC I/F: Low pin count interface.
4
PC hardware architecture II. Bus concept
1. Bus master: Device which owns control of a bus and is capable of issuing commands & target address during a master cycle.
J1 J2 J3
P CI S lo t 1
P CI S lo t 2
PCI Riser Board
P CI S lo t 3
PC hardware architecture
VIA MVP4 Family architecture
PBSRAM
CPU Socket 7
CRT
TAGRAM PCI Bus
RS232 DRIVER
PRINTER PORT
FDD
PS/2 K/B MOUSE
System BIOS
PC hardware architecture
INTEL 815 Family architecture
5V->3.3V 2.5V
U14 VCCID 2V
VRM HIP6016 VTT1.5V
U11 INTUE1L1 44I0NBTXEL
440BX
AGP BUS
66MHZ
14MHZ
U9 MGA MGA-G200A VGA CTRL_
33MHZ
66/100MHZ
ON BOARD VIDEO SGRAM
AUDIO CONNECTOR
HDD
CRYSTAL CSC4R28Y0 SPTCAIL AUDCISO42D8R0 IPVCEI AUDIO DRIVE
3. Bus cycle a. Memory read cycle: CPU (or bus master) reads data from memory b. Memory write cycle: CPU (or bus master) writes data to memory c. I/O read cycle: CPU (or bus master) reads data from I/O device d. I/O write cycle: CPU (or bus master) writes data to I/O device e. DMA cycle: Data is transferred between I/O device & memory directly under control of DMA controller without CPU intervention.
U16 Clock
Generator ICS9250-27
3.3V,2.5V
PCI CLK 33M 14.318M
48M
168Pin DIMM X2 SDRAMຫໍສະໝຸດ 3.3VDIMM1 DIMM2
J5 J6 J7
PCI Slots
CD ROM
HDD USB
U24
Firmware Hub
Intel 82802
HWQA培訓教材
PC hardware architecture PC 硬體架构
HWQA培訓教材
PC hardware architecture I. M/B block diagram
BIOS/
FLASH ROM
S
CPU
L O
T
1
PCI BUS
HDD
PCI DEVICE
CDROM
USB
ISA BUS
U8
I/O Controller Hub Intel FW82801 3.3V,1.8V
PCI Bus
U19
Audio ESS1938
5V
U15
Super I/O LPC47U332
5V,3V
J21
LPT
U14
J18
R S232 D rive r
S N7 5 1 8 5
C om Port
Audio Connector
2. Target (slave) device: Device which corresponds to the target address of a bus cycle and operates based on the commands from bus master.
5
PC hardware architecture
PCI SLOT1
33MHZ
ISA SLOT1
8MHZ 14.318MHZ
U21 BIOS/ FLASH ROM
PRINTER PORT
FDD
U21 FDC37M602
SUPER I/O CTRL_
PS/2 K/B
PS/2 MOUSE
14.318MHZ
SN75185 RS232 DRIVER
33MHZ
Driver
SN75185
J14
COM1 Port
J60
COM1 Port
J17
LPT
U1
Audio CS4299
J1
LAN connector
Audio Connector
ISA extension card Connector
PC hardware architecture . CPU: Central processor unit. L1 cache inside. . Host bus: Bus connected to CPU. . North bridge: Host to PCI bridge. Memory controller inside. . DIMM: Dual-in-line memory module. . VGA controller: Shows contents of video RAM on display. . South bridge: PCI to ISA bridge. Interrupt, DMA, Timer . PCI bus: 33MHz, 32-bit multiplexed address/data bus. . ISA bus: 24-bit address bus, 16-bit data bus. . Super I/O: FDC, SIO, PIO, KBC, RTC/CMOS inside. . ROM BIOS: System & video BIOS firmware codes inside.
5V->3.3V
U13
VRM
VCCID 2V
2.5V HIP6 VTT1.5V