EDA数字钟设计报告姓名： xxx学号：xxxxxxx专业：电子与通信工程日期：2014-11-7江苏科技大学电信院2014-11-71 引言数字钟通过数字电路技术实现时、分、秒计时，与机械钟相比具有更高的准确性和直观性，具有更长的使用寿命，已得到广泛的使用。

数字钟的设计方法有许多种，例如可用中小规模集成电路组成电子钟，也可以利用专用的电子钟芯片配以显示电路及其所需要的外围电路组成电子钟，还可以利用单片机来实现电子钟等等。

这些方法都各有其特点，本次电子线路课程设计是在vhdl基础上设计并制作一个可以调控的数字钟。

1．1 实验目的与要求1.1.1 实验目的（1）掌握GW48PK2++实验系统的基本用法以及vhdl语言的使用：（2）巩固元件例化、元件调用的基本方法，以及数码管、按键扫描的相关知识。

1.1.2实验要求（1）采用元件例化、元件调用实现整体设计；（2）利用按键进行调时；（3）能在实验箱进行仿真验证。

2 系统设计2.1 原理图设计数字钟原理图，如图1图1 数字钟原理图如图1所示，该系统主要包含六个模块，分为分频器、计数以及显示模块三大部分，另有按键进行时间控制。

2.2 各模块设计2.2.1分频器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity div isport(clk0:in std_logic;clk_1Hz,clk_1kHz:out std_logic);end entity;architecture one of div issignal q1Hz:integer range 0 to 10000000-1 ;signal q1kHz:integer range 0 to 10000-1 ;beginprocess(clk0)beginif clk0'event and clk0='1'thenif q1Hz<5000000-1 then clk_1Hz<='0';q1Hz<=q1Hz+1;elsif q1Hz=10000000-1 then q1Hz<=0;else clk_1Hz<='1';q1Hz<=q1Hz+1;end if;if q1kHz<5000-1 then clk_1kHz<='0';q1kHz<=q1kHz+1;elsif q1kHz=10000-1 then q1kHz<=0;else clk_1kHz<='1';q1kHz<=q1kHz+1;end if;end if;end process;end;该模块将10MHz的时钟进行分频，产生1S和1mS的信号传递给计数与显示部分。

2.2.2计数部分（1）60进制（秒，分——程序相同）entity cnt60s isport(clk,set:in std_logic;CLR:in std_logic:='0';--- d: in std_logic_vector(7 downto 0)co:out std_logic;h,l:buffer std_logic_vector(3 downto 0));end entity;architecture one of cnt60s issignal co1,set1 : std_logic;beginset1 <= set ;co <= (set1 or co1);process(clk,CLR)beginif CLR='1'thenh<="0000";l<="0000"; -----清零elseif clk'event and clk='1'then--if start='1' then-- h<=d(7 downto 4); -----十位为高4位-- l<=d(3 downto 0); -----个位为低4位if(h="0101" and l="1001")thenco1<='1';l<="0000";h<="0000";elseif l<"1001" thenl<=l+1;elsel<="0000";if h<"0101" thenh<=h+1;end if;end if;co1<='0';end if;end if;end if;end process;end;（2）24进制(时)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt24 isport(clk:in std_logic;CLR:in std_logic:='0';-- d: in std_logic_vector(7 downto 0) --- co:out std_logic;h,l:buffer std_logic_vector(3 downto 0)); end entity;architecture one of cnt24 isbeginprocess(clk,CLR)beginif CLR='1'thenh<="0000";l<="0000"; -----清零elsif clk'event and clk='1'then-- if start='1' then-- h<=d(7 downto 4); -----十位为高4位-- l<=d(3 downto 0); -----个位为低4位if h="0000"or h="0001" thenif l="1001" thenl<="0000";h<=h+1;elsel<=l+1;end if;elseif l="0011" thenl<="0000";if h="0010" thenh<="0000";elseh<=h+1;end if;elsel<=l+1;end if;end if;end if;end process;end;2.2.3显示部分（1）动态扫描library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity auto_cnt isport(clk:in std_logic;cnt: buffer integer range 0 to 7);end entity;architecture one of auto_cnt isbeginprocess(clk)beginif(clk'event and clk='1')thencnt<=cnt+1;end if;end process;end;（2）数码管显示library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity display isport(cnt:in integer range 0 to 7;hh,hl,mh,ml,sh,sl: in std_logic_vector(3 downto 0);sg: out std_logic_vector(6 downto 0);bt: out std_logic_vector(7 downto 0)); end entity;architecture one of display issignal a: integer range 0 to 10;beginP1:process(cnt,hh,hl,mh,ml,sh,sl)begincase cnt iswhen 0 => bt <= "00000001";a <= conv_integer(hh);when 1 => bt <= "00000010";a <= conv_integer(hl);when 2 => bt <= "00000100";a <= 10;----jiangefu"-"when 3 => bt <= "00001000";a <= conv_integer(mh);when 4 => bt <= "00010000";a <= conv_integer(ml);when 5 => bt <= "00100000";a <= 10;----jiangefu"-"when 6 => bt <= "01000000";a <= conv_integer(sh);when 7 => bt <= "10000000";a <= conv_integer(sl);when others => null;end case;end process P1;P2:process(a)begincase a iswhen 0 => sg <= "0111111";when 1 => sg <= "0000110";when 2 => sg <= "1011011";when 3 => sg <= "1001111";when 4 => sg <= "1100110";when 5 => sg <= "1101101";when 6 => sg <= "1111101";when 7 => sg <= "0000111";when 8 => sg <= "1111111";when 9 => sg <= "1101111";when 10 => sg <= "1000000";when others =>sg <= "1000000";end case;end process P2;end;2.2.4顶层文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity dclock isport(clk,s1,s0,k0:in std_logic;sg7: out std_logic_vector(6 downto 0);bt8: out std_logic_vector(7 downto 0));end entity;architecture one of dclock iscomponent divport(clk0:in std_logic;clk_1Hz,clk_1kHz:out std_logic);end component;component cnt60sport(clk,set:in std_logic;CLR:in std_logic:='0';--- d: in std_logic_vector(7 downto 0) co:out std_logic;h,l:buffer std_logic_vector(3 downto 0));end component;component cnt60mport(clk,set:in std_logic;CLR:in std_logic:='0';--- d: in std_logic_vector(7 downto 0)co:out std_logic;h,l:buffer std_logic_vector(3 downto 0));end component;component cnt24port(clk:in std_logic;CLR:in std_logic:='0';-- d: in std_logic_vector(7 downto 0)--- co:out std_logic;h,l:buffer std_logic_vector(3 downto 0));end component;component auto_cntport(clk:IN std_logic;cnt: buffer integer range 0 to 7);end component;component displayport(cnt:IN integer range 0 to 7;hh,hl,mh,ml,sh,sl: IN std_logic_vector(3 downto 0);sg: OUT std_logic_vector(6 downto 0);bt: OUT std_logic_vector(7 downto 0));end component;signal d,e,f,g:std_logic;signal m1,m0,n1,n0,p1,p0:std_logic_vector(3 downto 0);signal t:integer range 0 to 7;beginu1:div port map(clk0=>clk,clk_1Hz=>d,clk_1kHz=>e);u2:cnt60s port map(clk=>d,set=>s0,CLR=>k0,co=>f,h=>m1,l=>m0);u3:cnt60m port map(clk=>f,set=>s1,CLR=>k0,co=>g,h=>n1,l=>n0);u4:cnt24 port map(clk=>g,CLR=>k0,h=>p1,l=>p0);u5:auto_cnt port map(clk=>e,cnt=>t);u6:display port map(cnt=>t,hh=>m1,hl=>m0,mh=>n1,ml=>n0,sh=>p1, sl=>p0,sg=>sg7,bt=>bt8);end;3 实验结果与分析按下K2后，分钟加1，如图3所示，时间为00-04-09。