Slide - 17
A Scary Future
Smaller transistor channel lengths Short rise times Shorter design cycle times shorter rise times, higher clock frequencies signal integrity problems get worse designs must work the first time
TERMINATIONS
EMISSIONS ATTENUATION NON-MONOTONIC EDGES GROUND BOUNCE GROUND DISTRIBUTION SKIN DEPTH LOSSY LINES INDUCTANCE IR DROP LINE DELAY PARASITICS EMI/EMC SUSCEPTABILITY CAPACITANCE LOADED LINES POWER AND
What influences SSO Noise: Mutual inductance between the loops Number of SSOs dI/dt
Slide - 13
See additional Notes
Slide - 14
See additional Notes
CRITICAL NET
SIGNAL INTEGRITY TRANSMISSION LINES
RINGING
RETURN CURRENT PATH IMPEDANCE DISCONTINUITIES
CROSSTALK
STUB LENGTHS GAPS IN PLANES REFLECTIONS RC DELAY DISPERSION
(~ 50 Ohms)
Slide - 5
Signal Integrity Engineering is about Finding and Fixing Problems
3 inch long PCB Trace 3 inch long PCB Trace
Series termination (~40 Ohms)
Slide - 6
A Guiding Principle
In order to solve a signal integrity problem you must first understand its root cause
Slide - 7
Signal Integrity Initially Looks Confusing
Slide - 15
Projected Increase in Clock Frequencies
3500 3000
Microprocessor based products
Clock Frequency (MHz)
2500 2000 1500
on-chip
on-board
1000 500 0 1996
Slide - 2
Overview
“There are two kinds of design engineers, those that have signal integrity problems, and those that will” • The four signal integrity problems • Why signal integrity will get harder to solve • The right design methodology • The role of accurate, high bandwidth measurements • Two case studies: switching noise, probing
Design of Circuit based on Performance of Previous Design 5 Days Manufacture
Redesign 3 Days
One Cycle 9 Weeks Average 2 Cycles/Design
(CAD 2 Days) 4 Weeks
Slide - 4
General SI Problem #1:
• If the instantaneous impedance a signal sees ever changes, some of the signal will reflect and the rest will be distorted.
Example: Gold Dot Interconnect from Delphi
General Construction
Applications
Courtesy of Laurie Taira-Griffin, Delphi
Slide - 19
The Old Build it and Test it Design/Manufacturing Cycle
DELTA I NOISE
UNDERSHOOT, OVERSHOOT MODE CONVERSION
RISE TIME DEGRADATION
Slide - 8
The Four High Speed Problems
1. Signal quality of one net: reflections and distortions from impedance discontinuities in the signal or return path 2. Cross talk between multiple nets: mutual C and mutual L coupling with an ideal return path and without an ideal return path


“There are two kinds of design engineers, those that have signal integrity problems, and those that will”
So what’s the right design methodology?
Slide - 18
1998
2000
2002
2004
2006
2008
2010
2012
2014
Year
Source: SIA Roadmap
Slide - 16
High Speed Serial Link Applications Drive High Frequency
Hypertransport
AGP8x 3GIO
See additional Notes
Slide - 10
See additional Notes
Slide - 11
See additional Notes
Slide - 12
Conceptual Origin of Simultaneous Switching Output (SSO) Noise
• Ringing is often due to multiple reflections between impedance discontinuities at the ends
driver (low impedance)
3 inch long PCB Trace
receiver (high impedance)
• Critical processes for predicting signal integrity problems
Create equivalent circuit models for all components Simulate performance of components, critical nets and the whole system
Slide - 21
Role of Measurements
Verify a model and simulation from a calculation (anchor to reality)
Rules of thumb Analytic approximation Numerical tool: field solver, circuit simulation tool
On Chip
Icharge Idischarge
Active loop
Switching lines
Quiet data line
V SS V CC
Quiet loop
GND
L Bonding
common lead inductance
15836
L Bonding
Power
© 1991 Integrated Circuit Engineering Corporation
1.6 Gbps (400 MHz- 1.6 GHz)
2.1 Gbps (533 MHz) 2.5 Gbps (2 x 1.25 GHz)
Infiniband
OC-48 OC-192 RapidIO16 OC-768
2.5 Gbps (2.5 GHz)
2.488 Gbps ( 2.5 GHz) 9.953 Gbps ( 10 GHz) 32 Gbps (1 GHz, 16 bit mode) 39.81 Gbps ( 40 GHz)
Cross Section Confirm Physical Layout 2 Days
Test (TDR, VNA, BERT) 1-2 Weeks
Courtesy of Laurie Taira-Griffin, Delphi
SPICE Model 1 Week