Verilog编写的延时函数
用quartus编译通过，并口用modelsim进彳亍了后仿真老师让编写一个程序实现开关的延吋控制，具体要求是开关量变高电平后延吋500ms输出波形PWM1变为高，在延时500msPWM2输出波形变为高，在延时500msPWM3输出变为高电平。

当开关量变为低电平时，一次延时500ms, PWM3, PWM2, PWM1 一次变为高电平。

源程序如下：
module
testosc(osc_in, osc_out, clk_in, clk_out, input_signal, PWM1, PWM2, PWM3, sta rt, signal_buffcr); input osc_in, clk_in, input_signal;
output PWM1, PWM2, PWM3, start;
output osc_out, clk_out;
output signal_buffer;
reg
PWM1, PWM2, PWM3, osc_out, clk_out, start ;//outl, out2, out3, out4, out5, out6, out7, out& out9, outlO, outll, outl2, outl3, outl4, outl5, outl6, outl7, outl8, outl9, out20, out21, out22, out23, out24, out25, out26,out27,out2& out29,out 30,out31,out32;
rcg[10:0] count;
regsignal_buffer;
initial
begin
PWMl<=l，b0;
PWM2<=rbO;
PWM3<=rbO;
start<=r bO;
count〈二11' dO;
signal_buffer<=r bO;
end
always @(osc_in)
begin
if (osc_in二二1)
begin
osc_out<=0;
clk_out<=0;
end
el se
begin
osc_out〈二1;
clk_out<=l;
end
end
always ©(posedgeclkin)
begin
辻(input signal二二1' bO)
begin
case (count)
1T dO:if (signal_buffer==r bl)//distinguish the trigger signals start<=r bl;
else
start<=r bO;
ll，d2:PWM3<=l，bO;
ird4:PWM2<=rbO;
11' d6:begin
PWM1〈二1'bO;
start〈二1' bO;
sigrml_buffcr〈二1’bO; //remember the input signal
end
default:
begin
PWM1VPWM1;
PWM2<=PWM2;
PWM3<=PWM3;
end
endcase
end
else
begin
case (count)
1T dO: if (signal buffer二二1' bO)
start〈二1'bl;
else
start<=T bO;
ll，d2:PWMl<=l，bl;
ll'd4:PWM2Vl'bl;
1T d6:begin
PWM3〈二l'bl;
start<=r bO;
signal_buffer<=r bl;
end
default:
begin
PWM1<=PWM1;
PWM2<=PWM2;
PWM3〈二PWM3;
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endcase
end
end
always@(posedgeclk_in or negedge steirt) if (start==r bO) count 〈二11' dO;
else
if (count>lr dl500)
count<=lr dO;
else
count<=count+ir dl;
endmodule
quartus 仿真波形：
设计中用1K 的信号，因此舍弃了对输入信号input.signal 的检测，但是误差不 会大于1ms,可以忽略。

希望能帮到你们。

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Modelsim 仿真波形如.H ：。