1 一．程序代码及其仿真：
1． cnt60子模块代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY V_cnt60 IS
PORT ( clk :IN std_logic;
Q0,Q1,Q2,Q3,Q4,Q5,Q6,QC :OUT std_logic);
END V_cnt60;
ARCHITECTURE func OF V_cnt60 IS
SIGNAL count1 :std_logic_vector(3 downto 0);
SIGNAL count2 :std_logic_vector(3 downto 0);
SIGNAL carryin:std_logic;
BEGIN
Q0 <= count1(0);
Q1 <= count1(1);
Q2 <= count1(2);
Q3 <= count1(3);
Q4 <= count2(0);
Q5 <= count2(1);
Q6 <= count2(2);
QC <= carryin;
process(clk)
BEGIN
if (clk'event AND clk='1') then
carryin<='0';
if(count1="1001")then
count1<="0000";
count2<=count2+1;
else
count1<=count1+1;
END if;
if(count2="0101"AND count1="1001")then
count2<="0000";
count1<="0000";
carryin<='1';
END if;
END if;
END process;
END func;
cnt60仿真波形：
2
2． cnt24子模块代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY V_cnt24 IS
PORT ( clk :IN std_logic;
Q0,Q1,Q2,Q3,Q4,Q5:OUT std_logic);
END V_cnt24;
ARCHITECTURE func_cnt24 OF V_cnt24 IS
SIGNAL count1 :std_logic_vector(3 downto 0);
SIGNAL count2 :std_logic_vector(3 downto 0);
SIGNAL carryin:std_logic;
BEGIN
Q0 <= count1(0);
Q1 <= count1(1);
Q2 <= count1(2);
Q3 <= count1(3);
Q4 <= count2(0);
Q5 <= count2(1);
process(clk)
BEGIN
if (clk'event and clk='1') then
if(count1="1001")then
count1<="0000";
count2<=count2+1;
3 else
count1<=count1+1;
END if;
if(count2="0010" AND count1="0011")then
count2<="0000";
count1<="0000";
END if;
END if;
END process;
END func_cnt24;
cnt24仿真波形：
3． cnt1000字模块代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V_cnt1000 is
port( clk :in std_logic;
cnt1000 :out std_logic;
clk_c :out std_logic);
end V_cnt1000;
architecture bhv of V_cnt1000 is
signal tmp:std_logic_vector(9 downto 0);
signal amp:std_logic_vector(8 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1') then
4 if (tmp=1023)then tmp<="0000000000";
else tmp<=tmp+1;
end if;
if (tmp<511) then cnt1000<='0';
else cnt1000<='1';
end if;
end if;
end process;
process(clk)
begin
if (clk'event and clk='1') then
if (amp=511)then amp<="000000000";
else amp<=amp+1;
end if;
if (amp<255) then clk_c<='0';
else clk_c<='1';
end if;
end if;
end process;
end bhv;
cnt1000仿真波形：
4． clk_c子模块代码：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY V_clk_c IS
PORT
(clk,CLK_C,M1,S1,SS,MM,HH,CTRL : IN STD_LOGIC;
CLKS,CLKM,CLKH : OUT STD_LOGIC);
5 END V_clk_c;
ARCHITECTURE func OF V_clk_c IS
BEGIN
process
begin
CLKS<=(CTRL AND CLK) OR((NOT CTRL) AND HH AND MM AND (NOT
SS) AND CLK_C);
CLKM<=(CTRL AND S1) OR((NOT CTRL) AND HH AND (NOT MM) AND
SS AND CLK_C);
CLKH<=(CTRL AND M1) OR((NOT CTRL) AND (NOT HH) AND MM AND
SS AND CLK_C);
END process;
END func;
5． display子模块代码：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY display IS
PORT
( clk : IN std_logic;
LED1Q_0,LED1Q_1,LED1Q_2,LED1Q_3: IN std_logic;
LED2Q_0,LED2Q_1,LED2Q_2,LED2Q_3: IN std_logic;
LED3Q_0,LED3Q_1,LED3Q_2,LED3Q_3: IN std_logic;
LED4Q_0,LED4Q_1,LED4Q_2,LED4Q_3: IN std_logic;
LED5Q_0,LED5Q_1,LED5Q_2,LED5Q_3: IN std_logic;
LED6Q_0,LED6Q_1,LED6Q_2,LED6Q_3: IN std_logic;
LED1,LED2,LED3,LED4,LED5,LED6: OUT std_logic;
SE_A,SE_B,SE_C,SE_D,SE_E,SE_F,SE_G: OUT std_logic);
END display;
ARCHITECTURE func OF display IS
SIGNAL ctrl : std_logic_vector(2 downto 0);
SIGNAL code : std_logic_vector(3 downto 0);
BEGIN
process(ctrl)
BEGIN
CASE ctrl IS
WHEN "000"=> LED1<='1';
LED2<='0';
LED3<='0';
LED4<='0';
LED5<='0';
LED6<='0';
code(0)<=LED1Q_0;
code(1)<=LED1Q_1;
6 code(2)<=LED1Q_2;
code(3)<=LED1Q_3;
WHEN"001"=> LED1<='0';
LED2<='1';
LED3<='0';
LED4<='0';
LED5<='0';
LED6<='0';
code(0)<=LED2Q_0;
code(1)<=LED2Q_1;
code(2)<=LED2Q_2;
code(3)<=LED2Q_3;
WHEN "010"=> LED1<='0';
LED2<='0';
LED3<='1';
LED4<='0';
LED5<='0';
LED6<='0';
code(0)<=LED3Q_0;
code(1)<=LED3Q_1;
code(2)<=LED3Q_2;
code(3)<=LED3Q_3;
WHEN "011"=>LED1<='0';
LED2<='0';
LED3<='0';
LED4<='1';
LED5<='0';
LED6<='0';
code(0)<=LED4Q_0;
code(1)<=LED4Q_1;
code(2)<=LED4Q_2;
code(3)<=LED4Q_3;
WHEN "100"=>LED1<='0';
LED2<='0';
LED3<='0';
LED4<='0';
LED5<='1';
LED6<='0';
code(0)<=LED5Q_0;
code(1)<=LED5Q_1;
code(2)<=LED5Q_2;
code(3)<=LED5Q_3;
WHEN "101"=> LED1<='0';
LED2<='0';