实验三8位乘法器的设计一、实验目的1)了解8位乘法器的工作原理2)熟悉MAX+plusII软件的基本使用方法3)熟悉EDA实验开发的基本使用方法4)学习VHDL程序中数据对象，数据类型，顺序语句，并行语句的综合使用二、实验内容设计一个由8位加法器构成的以时序逻辑方式设计的8位乘法器。

其乘法原理是：乘法通过逐项位移相加原理来实现，以被乘数的最低位开始，若为1，则乘数左移后与上一次和相加，若为0，左移后以全零相加，直至被乘数的最高位。

三、实验条件开发软件：MAX+plus II 9.23 Baseline硬件设备：装有windows7的pc机四、实验设计1)系统的原理框架图2)VHDL源程序andarith.vhd源代码library ieee;use ieee.std_logic_1164.all;entity andarith isport(abin:in std_logic;din:in std_logic_vector(7 downto 0); dout: out std_logic_vector(7 downto 0)); end entity andarith;architecture art of andarith isbeginprocess(abin, din)isbeginfor i in 0 to 7 loopdout(i)<=din(i)and abin;end loop;end process;end architecture art;arictl.vhd源代码library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity arictl isport(clk:in std_logic; start: in std_logic; clkout:out std_logic; rstall: out std_logic; ariend: out std_logic);end entity arictl;architecture art of arictl issignal cnt4b:std_logic_vector(3 downto 0); beginrstall<=start;process(clk, start)isbeginif start='1' then cnt4b<="0000";elsif clk'event and clk='1'thenif cnt4b<8 thencnt4b<=cnt4b+1;end if;end if;end process;process (clk,cnt4b,start)isbeginif start='0'thenif cnt4b<8 thenclkout<=clk; ariend<='0';else clkout<='0'; ariend<='1';end if;else clkout<=clk; ariend<='0';end if;end process;end architecture art;sreg8b.vhdlibrary ieee;use ieee.std_logic_1164.all;entity sreg8b isport (clk: in std_logic;load: in std_logic;din: std_logic_vector(7 downto 0);qb: out std_logic);end entity sreg8b;architecture art of sreg8b issignal reg8:std_logic_vector(7 downto 0); beginprocess(clk, load)isbeginif clk'event and clk='1'thenif load='1'then reg8<=din;else reg8(6 downto 0)<=reg8(7 downto 1); end if;end if;end process;qb<=reg8(0);end architecture art;reg16b.vhdlibrary ieee;use ieee.std_logic_1164.all;entity reg16b isport(clk: in std_logic;clr: in std_logic;d: in std_logic_vector(8 downto 0);q: out std_logic_vector(15 downto 0));end entity reg16b;architecture art of reg16b issignal r16s: std_logic_vector(15 downto 0);beginprocess(clk,clr)isbeginif clr='1'then r16s<="0000000000000000";elsif clk'event and clk='1'thenr16s(6 downto 0)<=r16s(7 downto 1);r16s (15 downto 7)<=d;end if ;end process;q<= r16s ;end architecture art;Adder8b.vhd源代码library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder8b isport( c8:in std_logic;a8:in std_logic_vector(7 downto 0);b8: in std_logic_vector(7 downto 0);s8: out std_logic_vector(7 downto 0);co8: out std_logic);end entity adder8b ;architecture art of adder8b iscomponent adder4b isport(c4: in std_logic;a4: in std_logic_vector(3 downto 0);b4: in std_logic_vector(3 downto 0);s4: out std_logic_vector(3 downto 0);co4: out std_logic);end component adder4b;signal sc:std_logic;beginu1:adder4bport map(c4=>c8,a4=>a8(3 downto 0),b4=>b8(3 downto 0), s4=>s8(3 downto 0),co4=> sc);u2:adder4bport map(c4=>sc, a4=>a8(7 downto 4),b4=>b8(7 downto 4),s4=>s8(7 downto 4),co4=>co8);end architecture art;multi8x8.vhdlibrary ieee;use ieee.std_logic_1164.all;entity multi8x8 isport(clk: in std_logic;start: in std_logic;a: in std_logic_vector(7 downto 0);b: in std_logic_vector(7 downto 0);ariend: out std_logic;dout: out std_logic_vector(15 downto 0));end entity multi8x8;architecture art of multi8x8 iscomponent arictl isport(clk:in std_logic;start: in std_logic;clkout:out std_logic;rstall:out std_logic;ariend:out std_logic);end component arictl;component andarith isport(abin: in std_Logic;din: in std_logic_vector(7 downto 0);dout:out std_logic_vector(7 downto 0));end component andarith;component adder8b isport( c8:in std_logic;a8:in std_logic_vector(7 downto 0);b8: in std_logic_vector(7 downto 0);s8: out std_logic_vector(7 downto 0);co8: out std_logic);end component adder8b;component sreg8b isport (clk: in std_logic;load: in std_logic;din: std_logic_vector(7 downto 0);qb: out std_logic);end component sreg8b;component reg16b isport(clk: in std_logic;clr: in std_logic;d: in std_logic_vector(8 downto 0);q: out std_logic_vector(15 downto 0));end component reg16b;signal s1:std_logic;signal s2:std_logic;signal s3:std_logic;signal s4:std_logic;signal s5:std_logic_vector(7 downto 0);signal s6:std_logic_vector(8 downto 0);signal s7:std_logic_vector(15 downto 0);begindout<=s7;s1<='0';u1:arictl port map(clk=>clk,start=>start,clkout=>s2,rstall=>s3,ariend=>ariend);u2:sreg8b port map(clk=>s2,load=>s3,din=>a,qb=>s4);u3:andarith port map(abin=>s4,din=>b,dout=>s5);u4:adder8b port map(c8=>s1,a8=>s7(15 downto 8),b8=>s5,s8=>s6(7 downto 0),co8=>s6(8));u5:reg16b port map(clk=>s2,clr=>s3,d=>s6,q=>s7);end architecture art;3)管脚图五、实验结果及总结系统时序仿真结果从系统仿真结果可以看出，本系统完全符合设计要求，同时从仿真结果可以看出，从输入到输出有一定的延时，在11ns左右，这正是器件延时特征的反映。