3. 卷帶式接合(TAB—Tape Automatic Bonding)—使用金對金熱壓接合
Gold bond
註： TCP ( Tape Carrier Package ) 應用在LCD driver上。 Unimicron Technology (SuZhou) Corp. Do The Right Things.
5.
晶圓層級(Wafer-Level)
說明：所有封裝在Wafer完成後， 再Sawing
PI 聚亞矽氨
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3D Packages
Wireless Bonding ( FCB , others ) Wire Bonding
manufactured and delivered in a bare, or minimally packaged die format, which ＊ has quality and reliability comparable to its functionally equivalent packaged component, ＊ can be interconnected to its next level of packaging by wire bond, tape automated bonding, or flip-chip. 說明： 已知是好的Die封裝進度， Wafer sawing 無法100% 檢出IC是好是壞? 原因：
3. 協助排除耗熱 4. 保護電子零件 5. 建構人機介面
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常見之封裝形式
二面出腳
DIP 挿件式 ( Dual In-Line Package )
四面出腳
PLCC ( Plastic Leaded Chip Carrier )
5
單晶片構裝之基本結構
膠體 ( Epoxy Molding Compound )
晶片(Chip) 金線(Gold Wire) 引腳(Lead)
晶片座(Die Pad)
銀膠(Silver Epoxy)
優點：膠體對稱，不易產生翹曲
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單晶片構裝之演變
PTH → SMT → Area Array → Fine Pitch Area Array
Direct Chip Attach on Board * 一定要使用較小的 IC (CTE過大易裂 )
Chip Scale Package
BGA
Wire Bond ↓ Flip Chip 的應用
Plastic Tape Ceramic
類別 基板 膠體結構
PBGA
BT樹脂 Over mold Glob Top Cap 7~50 mm Up / Down Solder Ball 63Sn / 37pb 1.0/1.27/1.5 7.2
TBGA
Polyimide Optional Cap
CBGA
21~40 mm Up Solder Ball 10Sn / 90pb 1.0/1.27/1.5 5.3
18~32 mm Up / Down Solder Ball 10Sn / 90pb 1.0/1.27/1.5 4.5
32~42.5mm Up / Down Solder Column 10Sn / 90pb 1.0/1.27/1.5 4.5
4. 無引腳 (Non Lead)
QFN(Quad Flat Non-lead)
5. 晶片座 (Die Pad)
優點：1. 散熱能力佳
2. 面積小(無須預留接腳空間)
3. 傳輸距離短 4. 無腳彎翹風險 缺點：Molding 困難度較高 (不對稱，易發生翹曲 ) Unimicron Technology (SuZhou) Corp.
多層陶瓷 Optional Cap
CCGA
多層陶瓷 Optional Cap
Micro BGA
Optional Over mold Glob Top Optional Cap Chip Scale Up / Down Metal Ball Solder / Gold 0.8/0.5 1~1.4
膠體尺寸 晶片方向 錫球 間距 面積效率 (Chip=1)
6
BGA(Ball Grid Array)構造
Second bonding Bonding pattern Solder resist Chip First bonding Mold compound Ag paste
Gold wire
Ground Solder balls
Solder pattern Thermal via hole
SOP SMD device ( Small Outline Package )
QFP ( Quad Flat Pack )
SOJ ( Small Outline J-Lead )
PGA ( Pin Grid Array )
PBGA (Plastic ball Grid Array)
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模組板
Module board
主機板(母板)
Mother board
多晶片模組
( MCM ： Multi-Chips
Module )
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電子構裝之主要功能
1. 有效供應電源
2. 提供信號傳輸
＊ CSP is derived from existing packages, that is, it can be any type of packages.
覆晶(Flip Chip) 技術
＊
表面黏著技術 (Surface Mount) Chip Scale 構裝
＊
Silicon
標準化 定義：
小尺寸
De-Taping
Singulation Wafer Sawing
Substrate pre-bake
Molding
Top Marking & Curing
(Punch or Routing)
Die Bonding
Curing
Ball Mount
Ball Scan
應用產品：電腦、通訊、電子消費性產品
所需技術
電子、機械、物理、化學、材料、光學、可靠性工程、人 因工程…等多重之工程技術。
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2
電子構裝之分級
晶圓(Wafer) → 晶片(Chip) →第一階層封裝 → 第二階層封裝 → 第三階層封裝 單晶片構裝
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PBGA Assembly Process
Wafer Incoming
Taping
Wire Bonding
Interconnecting 完成 O/S Test or 3rd Vision Insp. Plasma Clean
Flux Clean
Wafer Grinding
PGA TO 1970 DIP QFP 1980
TCP
1.電訊上的考慮(速度、 傳輸路徑短 ) 2. IO數的考量(IO數 較Ball Pad受限) 1990 2000 2010
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BGA構裝之分類
Chip Chip Chip
Chip
Chipቤተ መጻሕፍቲ ባይዱ
Single Chip Module
Multi Chip Module
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What is KGD?
＊ Known Good Die (KGD) is a which has been
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CSP(Chip Scale Package)
＊ Definition： Chip scale package (CSP) is a package whose package-to-silicon area ratio less than 120 percent.
1.
2.
檢驗困難度高
成本貴
大部份的是IC封完後測出IC是好是壞?
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封裝製程介紹
IC Assembly Process Introduction
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CSP之分類
1. 硬板中介層(Rigid Substrate Interposer)
2.
導線架形式(Leadframe Type)
3.
軟板中介層(Flex circuit Interposer)
4.
無中介層， 壓模成型(Transfer Molding)