数字电路实验报告一
4-bit Full Adder Design
1.1 Requirement of the Experiment
Design a 4-bite Adder to add A(A3A2A1A0) and B(B3B2B1B0),output 4-bit Sum S=A+B and the COUT as the carry.
1.2 Experiment Target
1. Learn the Logic Diagram Input Method with ispDesignLEVER.
2. Understand how to deisgn a test vector file in ABEL-HDL.
3. To be familiar with the PLD Experiment System(PLD-PAC-1).
4. To know the drawing method of Logic Diagram in ispDesignLEVER and its function simulation process.
5. Know the principles and structure of 4-bit Ripple Adder.
1.3 Step of Experiment
1. Use Schematic Editor to input the logic diagram of a 4-bit adder(*.sch)
2. Input the ABEL-HDL test vector file(*.abv)
3.Do the function simulation with the above test vector and check the output vaild according to the waveforms until to error happens.
4.Specify the input and output Pin No. by connecting I/O PAD to input and output of above 4-bit adder. Switch S8-S5(34-37)and S4-S1(38-41)on PLD Experimental System can be used as input A and B,LED6(18-15 ) and
LED5(14-11) as the output S(Sum). L8 can be used to show the carry (Cout).Note that L1-L8(83-76) is active-low.
5.Do the Fit Design function to generate the circuit JED file.
6.Download the JED into the chip on PLD Experiment System and verify the results.
1.4 Experiment Content
Circuit Diagram(*.sch)
Circuit Test Vector(*.abv)
Circuit Function Simulation Results including the critical
waveforms。